Document
HD74LS78A
Dual J-K Flip-Flops (with Preset, Common Clear, and Common Clock)
Features
• Ordering Information
REJ03D0419–0300 Rev.3.00
Jul.22.2005
Part Name
Package Type
Package Code Package (Previous Code) Abbreviation
HD74LS78AFPEL SOP-14 pin (JEITA)
PRSP0014DF-B (FP-14DAV)
FP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation (Quantity)
EL (2,000 pcs/reel)
Pin Arrangement
CK 1
1PR 2
1J 3
VCC CLR
4 5
2PR 6
2K 7
K CK J CLR PR
QQ
K CK J CLR PR
QQ
14 1K 13 1Q 12 1Q 11 GND 10 2J 9 2Q 8 2Q
(Top view)
Function Table
Inputs
Outputs
Preset
Clear
Clock
J
K
Q
Q
L H X XX H L
H L X XX L H
L L X X X H* H*
H H ↓ L L Q0 Q0
H H ↓ HL H L
H H ↓ LH L H
H H ↓ HH
Toggle
H H H X X Q0 Q0
Notes: H; high level, L; low level, X; irrelevant, ↓; transition from high to low level, Q0; level of Q before the indicated steady-state input conditions were established. Q0; complement of Q0 or level of Q before the indicated.