Octal D-type Flip-Flops with 3-state Outputs
Feb. 01, 2005
The HD74LV574A has eight edge trigger D type flip flops with three state outputs in a 20 pin package. Data at the D
inputs meeting set up requirements, are transferred to the Q outputs on positive going transitions of the clock input.
When the clock input goes low, data at the D inputs will be retained at the outputs until clock input returns high again.
When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of
what signals are present at the other inputs and the state of the storage elements. Low-voltage and high-speed operation
is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
• Output current ±8 mA (@VCC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V)
• Ordering Information
(Previous Code) Abbreviation
SOP–20 pin (JEITA) PRSP0020DD–B
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Note: H: High level
L: Low level
Z: High impedance
Q0: Output level before the indicated steady state input conditions were established.
Rev.1.00 Feb. 01, 2005 page 1 of 7