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HD74ALVCH16721 Dataheets PDF



Part Number HD74ALVCH16721
Manufacturers Renesas
Logo Renesas
Description 3.3-V 20-bit Flip Flops
Datasheet HD74ALVCH16721 DatasheetHD74ALVCH16721 Datasheet (PDF)

HD74ALVCH16721 3.3-V 20-bit Flip Flops with 3-state Outputs REJ03D0035-0400Z (Previous ADE-205-139B (Z)) Rev.4.00 Oct.02.2003 Description The HD74ALVCH16721’s twenty flip flops are edge triggered D-type flip flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs, provided that the clock enable (CLKEN) input is low. If CLKEN is high, no data is stored. A buffered output enable (OE) input can be used to place the twen.

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HD74ALVCH16721 3.3-V 20-bit Flip Flops with 3-state Outputs REJ03D0035-0400Z (Previous ADE-205-139B (Z)) Rev.4.00 Oct.02.2003 Description The HD74ALVCH16721’s twenty flip flops are edge triggered D-type flip flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs, provided that the clock enable (CLKEN) input is low. If CLKEN is high, no data is stored. A buffered output enable (OE) input can be used to place the twenty outputs in either a normal logic state (high or low level) or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly. The high impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The output enable (OE) input does not affect the internal operation of the flip flops. Old data can be retained or new data can be entered while the outputs are in the high impedan.


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