Express Switch. 89HPES24T6G2 Datasheet

89HPES24T6G2 Switch. Datasheet pdf. Equivalent


IDT 89HPES24T6G2
24-Lane 6-Port
Gen2 PCI Express® Switch
®
89HPES24T6G2
Data Sheet
Device Overview
The 89HPES24T6G2 is a member of IDT’s PRECISE™ family of PCI
Express® switching solutions. The PES24T6G2 is a 24-lane, 6-port
Gen2 peripheral chip that performs PCI Express base switching with a
feature set optimized for high performance applications such as servers,
storage, and communications systems. It provides connectivity and
switching functions between a PCI Express upstream port and up to five
downstream ports and supports switching between downstream ports.
Features
High Performance PCI Express Switch
– Twenty-four 5 Gbps Gen2 PCI Express lanes supporting
5 Gbps and 2.5 Gbps operation
– Up to six switch ports
– Support for Max Payload Size up to 2048 bytes
– Supports one virtual channel and eight traffic classes
– Fully compliant with PCI Express base specification Revision
2.0
Flexible Architecture with Numerous Configuration Options
– Automatic per port link width negotiation to x8, x4, x2, or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion
– Supports in-band hot-plug presence detect capability
– Supports external signal for hot plug event notification allowing
SCI/SMI generation for legacy operating systems
– Dynamic link width reconfiguration for power/performance
optimization
– Configurable downstream port PCI-to-PCI bridge device
numbering
– Crosslink support
– Supports ARI forwarding defined in the Alternative Routing-ID
Interpretation (ARI) ECN for virtualized and non-virtualized
environments
– Ability to load device configuration from serial EEPROM
Legacy Support
– PCI compatible INTx emulation
– Supports bus locked transactions, allowing use of PCI Express
with legacy software
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates twenty-four 5 Gbps / 2.5 Gbps embedded SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
– Ability to disable peer-to-peer communications
– Supports ECRC and Advanced Error Reporting
– All internal data and control RAMs are SECDED ECC
protected
– Supports PCI Express hot-plug on all downstream ports
– Supports upstream port hot-plug
Block Diagram
Frame Buffer
6-Port Switch Core / 24 Gen2 PCI Express Lanes
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
(Port 0)
(Port 1)
Figure 1 Internal Block Diagram
2013 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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89HPES24T6G2 Datasheet
Recommendation 89HPES24T6G2 Datasheet
Part 89HPES24T6G2
Description 24-Lane 6-Port Gen2 PCI Express Switch
Feature 89HPES24T6G2; 24-Lane 6-Port Gen2 PCI Express® Switch ® 89HPES24T6G2 Data Sheet Device Overview The 89HPES24T6G2.
Manufacture IDT
Datasheet
Download 89HPES24T6G2 Datasheet




IDT 89HPES24T6G2
IDT 89HPES24T6G2 Data Sheet
– Hot-swap capable I/O
– External Serial EEPROM contents are checksum protected
– Supports PCI Express Device Serial Number Capability
– Capability to monitor link reliability and autonomously change
link speed to prevent link instability
Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Support PCI Power Management Interface specification (PCI-
PM 1.1)
• Supports device power management states: D0, D3hot and
D3cold
– Support for PCI Express Active State Power Management
(ASPM) link state
• Supports link power management states: L0, L0s, L1, L2/L3
Ready and L3
– Supports PCI Express Power Budgeting Capability
– Configurable SerDes power consumption
• Supports optional PCI-Express SerDes Transmit Low-Swing
Voltage Mode
• Supports numerous SerDes Transmit Voltage Margin
settings
– Unused SerDes are disabled
Testability and Debug Features
– Per port link up and activity status outputs available on I/O
expander outputs
– Built in SerDes 8-bit and 10-bit pseudo-random bit stream
(PRBS) generators
– Numerous SerDes test modes, including a PRBS Master
Loopback mode for in-system link testing
– Ability to read and write any internal register via SMBus and
JTAG interfaces, including SerDes internal controls
– Per port statistics and performance counters, as well as propri-
etary link status registers
Eleven General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Option A Package: 19mm x 19mm 324-ball Flip Chip BGA
with 1mm ball spacing
Option B Package: 27mm x 27mm 676-ball Flip Chip BGA
with 1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES24T6G2
provides the most efficient I/O connectivity solution for applications
requiring high throughput, low latency, and simple board layout with a
minimum number of board layers. It provides connectivity for up to 6
ports across 24 integrated serial lanes. Each lane provides 5 Gbps of
bandwidth in both directions and is fully compliant with PCI Express
Base Specification, Revision 2.0, including operation in 5 Gbps, 2.5
Gbps, and mixed 5 Gbps / 2.5Gbps modes.
The PES24T6G2 is based on a flexible and efficient layered architec-
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 2.0. The PES24T6G2 can operate either as a store and
forward or cut-through switch and is designed to switch memory and I/O
transactions. It supports eight Traffic Classes (TCs) and one Virtual
Channel (VC) with sophisticated resource management to enable effi-
cient switching and I/O connectivity for servers, storage, and embedded
processors with limited connectivity.
Processor
Processor
North
Bridge
x8
MMMeMemememomororyoyrryy
PES24T6G2
x4
x4 x4
x4
PCI Express
Slots
I/O
10GbE
I/O
10GbE
I/O
SATA
I/O
SATA
Figure 2 I/O Expansion Application
SMBus Interface
The PES24T6G2 contains two SMBus interfaces. The slave inter-
face provides full access to the configuration registers in the
PES24T6G2, allowing every configuration register in the device to be
read or written by an external agent. The master interface allows the
default configuration register values of the PES24T6G2 to be over-
ridden following a reset with values programmed in an external serial
EEPROM. The master interface is also used by an external Hot-Plug I/O
expander.
Six pins make up each of the two SMBus interfaces. These pins
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the
SMBus address to which the device responds to be configured. In the
master interface, these address pins allow the SMBus address of the
serial configuration EEPROM from which data is loaded to be config-
ured. The SMBus address is set up on negation of PERSTN by
sampling the corresponding address pins. When the pins are sampled,
the resulting address is assigned as shown in Table 1.
Note: MSMBADDR and SSMBADDR address pins are not
available in the 19mm package. The MSMBADDR address is
hardwired to 0x50, and the SSMBADDR address is hardwired
to 0x77.
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IDT 89HPES24T6G2
IDT 89HPES24T6G2 Data Sheet
Slave
Master
Bit
SMBus
SMBus
Address
Address
1
SSMBADDR[1]
MSMBADDR[1]
2
SSMBADDR[2]
MSMBADDR[2]
3
SSMBADDR[3]
MSMBADDR[3]
4 0 MSMBADDR[4]
5 SSMBADDR[5]
1
61
0
71
1
Table 1 Master and Slave SMBus Address Assignment for 27x27mm Package
As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure
3(a), the master and slave SMBuses are tied together and the PES24T6G2 acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES24T6G2 registers supports SMBus arbitration. In some systems, this SMBus
master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To
support these systems, the PES24T6G2 may be configured to operate in a split configuration as shown in Figure 3(b).
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
The PES24T6G2 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of
the serial EEPROM.
PES24T6G2
Processor
SMBus
Master
...Serial
EEPROM
Other
SMBus
Devices
PES24T6G2
...Processor
SMBus
Other
SMBus
Master
Devices
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
Serial
EEPROM
(a) Unified Configuration and Management Bus
(b) Split Configuration and Management Buses
Figure 3 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES24T6G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES24T6G2
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura-
tion, whenever the state of a Hot-Plug output needs to be modified, the PES24T6G2 generates an SMBus transaction to the I/O expander with the
new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN
input pin (alternate function of GPIO) of the PES24T6G2. In response to an I/O expander interrupt, the PES24T6G2 generates an SMBus transaction
to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES24T6G2 provides General Purpose Input/Output (GPIO) pins (7 pins in the 19mm package and 11 pins in the 27mm package) that may be
used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software control. Many
GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus slave interface, or serial configura-
tion EEPROM.
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