SERIALCMOS EEPROM. IS24C256 Datasheet

IS24C256 EEPROM. Datasheet pdf. Equivalent


ISSI IS24C256
IS24C256
262,144-bit 2-WIRE SERIAL
CMOS EEPROM
FEATURES
• Organization:
– 32K-bit x 8-bit
• 64-Byte Page Write Buffer
• Two-Wire Serial Interface
– Bi-directional data transfer protocol
• Low Power CMOS Technology
– Active Current less than 3 mA (5V)
– Standby Current less than 6 µA (5V)
– Standby Current less than 2 µA (2.5V)
• Wide Voltage Operation
– IS24C256-2: Vcc = 1.8V to 5.5V
– IS24C256-3: Vcc = 2.5V to 5.5V
• 1 MHz (I2CTM Protocol) Compatibility
• Hardware Data Protection
– Write Protect pin
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• Self time Write cycle with auto clear
– 5 ms @ 5.0V
• High Reliability
– Endurance: 100,000 Cycles
– Data Retention: 40 Years
• Commercial and Industrial temperature ranges
• 8-pin PDIP, 8-pin SOIC, and 14-pin TSSOP
ISSI®
DESCRIPTION
ADVANCED INFORMATION
MARCH 2003
The IS24C256 is an electrically erasable PROM device
that uses the standard 2-wire interface for
communications. The IS24C256 contains a memory
array of 256K-bits (32,768 x 8), and is further
subdivided into 512 pages of 64 bytes each for Page-
Write mode. This EEPROM is offered in wide operating
voltages of 1.8V to 5.5V (IS24C256-2) and 2.5V to 5.5V
(IS24C256-3) to be compatible with most application
voltages. ISSI designed the IS24C256 to be a low-cost
and low-power 2-wire EEPROM solution. The devices
are packaged in 8-pin PDIP, 8-pin SOIC, and 14-pin
TSSOP.
The IS24C256 maintains compatibility with the popular
2-wire bus protocol, so it is easy to design into
applications implementing this bus type. The simple
bus consists of the Serial Clock wire (SCL) and the
Serial Data wire (SDA). Using the bus, a Master device
such as a microcontroller is usually connected to one
or more Slave devices such as the IS24C256. The bit
stream over the SDA line includes a series of bytes,
which identifies a particular Slave device, an
instruction, an address within that Slave device, and a
series of data, if appropriate. The IS24C256 has a Write
Protect pin (WP) to allow blocking of any write
instruction transmitted over the bus.
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00B
03/11/03
1


IS24C256 Datasheet
Recommendation IS24C256 Datasheet
Part IS24C256
Description 2-WIRE SERIALCMOS EEPROM
Feature IS24C256; IS24C256 262,144-bit 2-WIRE SERIAL CMOS EEPROM FEATURES • Organization: – 32K-bit x 8-bit • 64-Byte .
Manufacture ISSI
Datasheet
Download IS24C256 Datasheet




ISSI IS24C256
IS24C256
FUNCTIONAL BLOCK DIAGRAM
Vcc
SDA
SCL
WP
A0
A1
A2
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
WORD ADDRESS
COUNTER
GND
nMOS
ACK
ISSI®
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
EEPROM
ARRAY
Y
DECODER
Clock
DI/O
> DATA
REGISTER
2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
03/11/03



ISSI IS24C256
IS24C256
PIN CONFIGURATION
8-Pin DIP and SOIC
A0 1
A1 2
A2 3
GND 4
8 VCC
7 WP
6 SCL
5 SDA
ISSI®
14-pin TSSOP
A0
A1
A2
NC
NC
NC
GND
1
2
3
4
5
6
7
14 VCC
13 WP
12 NC
11 NC
10 NC
9 SCL
8 SDA
PIN DESCRIPTIONS
A0-A2
SDA
SCL
WP
Vcc
NC
GND
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
No Connect
Ground
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an open
drain output and can be wire Or'ed with other open drain
or open collector outputs. The SDA bus requires a pullup
resistor to Vcc.
A0, A1, A2
The A0, A1, and A2 are the device address inputs that are
hardwired or left not connected for hardware compatibility
with the IS24C32/64/128. When pins are hardwired, as
many as eight 256K devices may be addressed on a single
bus system. When the pins are not hardwired, the default
A0, A1, and A2 are zero.
WP
WP is the Write Protect pin. If the WP pin is tied to Vcc
the entire array becomes Write Protected (Read only).
When WP is tied to GND or left floating, normal read/write
operations are allowed to the device.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
03/11/03
3







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