STATIC RAM. IS61SP25618 Datasheet

IS61SP25618 RAM. Datasheet pdf. Equivalent


ISSI IS61SP25618
IS61SP25616
IS61SP25618
256K x 16, 256K x 18 SYNCHRONOUS
PIPELINED STATIC RAM
ISSI®
APRIL 2001
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Single +3.3V, +10%, -5% power supply
• Power-down snooze mode
DESCRIPTION
The ISSI IS61SP25616 and IS61SP25618 is a high-speed
synchronous static RAM designed to provide a burstable,
high-performance memory for high speed networking and
communication applications. It is organized as 262,144
words by 16 bits and 18 bits, fabricated with ISSI's
advanced CMOS technology. The device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-8, BW2 controls DQ9-16, conditioned
by BWE being LOW. A LOW on GW input would cause all
bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
-166
3.5
6
166
-150 -133
3.8 4
6.7 7.5
150 133
-5 Units
5 ns
10 ns
100 MHz
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
1


IS61SP25618 Datasheet
Recommendation IS61SP25618 Datasheet
Part IS61SP25618
Description 256K x 16 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM
Feature IS61SP25618; IS61SP25616 IS61SP25618 256K x 16, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM ISSI® APRIL 2001 FEA.
Manufacture ISSI
Datasheet
Download IS61SP25618 Datasheet




ISSI IS61SP25618
IS61SP25616
IS61SP25618
BLOCK DIAGRAM
MODE
ADV
CLK
ADSC
ADSP
A2-A17
A1
A0
GW
BWE
BW1
BW2
CE1
CE2
CE2
OE
2
ISSI ®
CLK2
ADDRESS
REGISTER
BURST
COUNTER
CLR
2 18
256K x 16/256K x 18
MEMORY ARRAY
2
18
16
16 or 18
16 or 18
BW1
BYTE WRITE
REGISTER
BW2
BYTE WRITE
REGISTER
CLK2
2
CLK
DATA
INPUT
REGISTER
DATA
OUTPUT
REGISTER
CLK
ENABLE
REGISTER
ENABLE
REGISTER
DQ1 - DQ16
or
DQ1 - DQ18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01



ISSI IS61SP25618
IS61SP25616
IS61SP25618
PIN CONFIGURATION
119-pin PBGA (Top View)
1234567
A
VCCQ
A6
A4 ADSP A8
B
NC CE2 A3 ADSC A9
C
NC A7 A2 VCC A12
D
DQ9 NC GND NC GND
E
NC DQ10 GND CE GND
F
VCCQ NC GND OE GND
G
NC DQ11 BW2 ADV GND
H
DQ12 NC GND GW GND
J
VCCQ VCC NC VCC NC
K
NC DQ13 GND CLK GND
L
DQ14 NC GND NC BW1
M
VCCQ DQ15
GND
BWE
GND
N
DQ16 NC GND A1 GND
P
NC
NC GND A0 GND
R
NC
A5 MODE VCC
NC
T
NC A11 A10 NC A14
U
VCCQ NC NC NC NC
A16 VCCQ
CE2 NC
A15 NC
NC NC
NC DQ8
DQ7 VCCQ
NC DQ6
DQ5
NC
VCC VCCQ
NC DQ4
DQ3
NC
NC VCCQ
DQ2
NC
NC DQ1
A13 NC
A17 ZZ
NC VCCQ
ISSI ®
100-Pin TQFP
NC
NC
NC
VCCQ
GND
NC
NC
DQ9
DQ10
GND
VCCQ
DQ11
DQ12
NC
VCC
NC
GND
DQ13
DQ14
VCCQ
GND
DQ15
DQ16
NC
NC
GND
VCCQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A17
NC
NC
VCCQ
GND
NC
NC
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
NC
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
NC
GND
VCCQ
NC
NC
NC
256K x 16
PIN DESCRIPTIONS
A0, A1
A2-A17
CLK
ADSP
ADSC
ADV
BW1-BW2
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQ1-DQ16 Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND
Ground
VCCQ
Isolated Output Buffer Supply: +3.3V
ZZ Snooze Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
3







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