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BSP100 Dataheets PDF



Part Number BSP100
Manufacturers NXP
Logo NXP
Description N-channel enhancement mode TrenchMOS transistor
Datasheet BSP100 DatasheetBSP100 Datasheet (PDF)

Philips Semiconductors Product specification N-channel enhancement mode TrenchMOS™ transistor FEATURES • ’Trench’ technology • Low on-state resistance • Fast switching • High thermal cycling performance • Low thermal resistance BSP100 SYMBOL d QUICK REFERENCE DATA VDSS = 30 V ID = 6 A g RDS(ON) ≤ 100 mΩ (VGS = 10 V) RDS(ON) ≤ 200 mΩ (VGS = 4.5 V) s GENERAL DESCRIPTION N-channel enhancement mode field-effect transistor in a plastic envelope using ’trench’ technology. Applications:• Motor a.

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Philips Semiconductors Product specification N-channel enhancement mode TrenchMOS™ transistor FEATURES • ’Trench’ technology • Low on-state resistance • Fast switching • High thermal cycling performance • Low thermal resistance BSP100 SYMBOL d QUICK REFERENCE DATA VDSS = 30 V ID = 6 A g RDS(ON) ≤ 100 mΩ (VGS = 10 V) RDS(ON) ≤ 200 mΩ (VGS = 4.5 V) s GENERAL DESCRIPTION N-channel enhancement mode field-effect transistor in a plastic envelope using ’trench’ technology. Applications:• Motor and relay drivers • d.c. to d.c. converters • Logic level translator The BSP100 is supplied in the SOT223 surface mounting package. PINNING PIN 1 2 3 4 gate drain source drain (tab) DESCRIPTION SOT223 4 1 2 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 ˚C to 150˚C Tj = 25 ˚C to 150˚C; RGS = 20 kΩ Tsp = 25 ˚C Tsp = 100 ˚C Tamb = 25 ˚C Tsp = 25 ˚C Tsp = 25 ˚C MIN. - 65 MAX. 30 30 ± 20 61 4.4 3.2 24 8.3 150 UNIT V V V A A A A W ˚C THERMAL RESISTANCES SYMBOL Rth j-sp Rth j-amb PARAMETER Thermal resistance junction to solder point Thermal resistance junction to ambient CONDITIONS surface mounted, FR4 board surface mounted, FR4 board TYP. 12 70 MAX. 15 UNIT K/W K/W 1 Continuous current rating limited by package February 1999 1 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOS™ transistor AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS IAS Non-repetitive avalanche energy Non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 6 A; tp = 0.2 ms; Tj prior to avalanche = 25˚C; VDD ≤ 15 V; RGS = 50 Ω; VGS = 10 V MIN. - BSP100 MAX. 23 6 UNIT mJ A ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) gfs ID(ON) IDSS IGSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 10 µA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 150˚C Tj = -55˚C VGS = 10 V; ID = 2.2 A VGS = 4.5 V; ID = 1 A VGS = 10 V; ID = 2.2 A; Tj = 150˚C Forward transconductance VDS = 20 V; ID = 2.2 A On-state drain current VGS = 10 V; VDS = 1 V; VGS = 4.5 V; VDS = 5 V Zero gate voltage drain VDS = 24 V; VGS = 0 V; current VDS = 24 V; VGS = 0 V; Tj = 150˚C Gate source leakage current VGS = ±20 V; VDS = 0 V Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 2.3 A; VDD = 15 V; VGS = 10 V MIN. 30 27 1 0.4 2 3.5 2 TYP. MAX. UNIT 2 80 120 4.5 10 0.6 10 6 0.7 0.7 6 8 21 15 2.5 5 250 88 54 2.8 3.2 100 200 170 100 10 100 V V V V V mΩ mΩ mΩ S A A nA µA nA nC nC nC ns ns ns ns nH nH pF pF pF VDD = 20 V; RD = 18 Ω; VGS = 10 V; RG = 6 Ω Resistive load Measured tab to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 20 V; f = 1 MHz February 1999 2 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOS™ transistor REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Tsp = 25 ˚C MIN. IF = 1.25 A; VGS = 0 V IF = 1.25 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 25 V - BSP100 TYP. MAX. UNIT 0.82 69 55 6 24 1.2 A A V ns nC 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating 100 Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID tp = 10 us 10 100 us d.c. 1 ms 10 ms 100 ms BSP100 1 0.1 0 20 40 60 80 Tsp / C 100 120 140 1 10 Drain-Source Voltage, VDS (V) 100 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tsp) Fig.3. Safe operating area. Tsp = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp 120 110 100 90 80 70 60 50 40 30 20 10 0 ID% Normalised Current Derating 100 Peak Pulsed Drain Current, IDM (A) BSP100 10 D = 0.5 0.2 1 0.1 0.05 P D tp D = tp/T 0.1 0.02 single pulse T 1E-03 1E-02 1E-01 1E+00 1E+01 0.01 1E-06 1E-05 1E-04 0 20 40 60 80 100 Tsp / C 120 140 Pulse width, tp (s) Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tsp); conditions: VGS ≥ 10 V Fig.4. Transient thermal impedance. Zth j-sp = f(t); parameter D = tp/T February 1999 3 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOS™ transistor BSP100 6 Drain Current, ID (A) 10 9 8 7 6 5 4 3 2 1 0 0 0.2.


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