MT28EW128ABA

128Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR Features Parallel NOR Flash Embedded Memory MT28EW128ABA Features Single-level cell (SLC) process technology Density: 128Mb Supply voltage – VCC = 2.7–3.6V (program, erase, read) – VCCQ = 1.65 - VCC (I/O buffers) Asynchronous random/page read – Page size: 16 words or 32 bytes – Page access: 20ns – Random access: 70ns (VCC = VCCQ = 2.7-3.6V) – Random access: 75ns (VCCQ = 1.65-VCC) Buffer program (512-word program buffer) – 2.0 MB/s (TYP) when using full buffer program – 2.5 MB/s (TYP) when using accelerated buffer program (VHH) Word/Byte program: 25us per word (TYP) Block erase (128KB): 0.2s (TYP) Memory organization – Uniform blocks: 128KB or 64KW each – x8/x16 data bus Program/erase suspend and resume capability – Read from another block during a PROGRAM SUSPEND operation – Read or program another block during an ERASE SUSPEND operation Unlock bypass, block erase, chip erase, and write to buffer capability BLANK CHECK operation to verify an erased block CYCLIC REDUNDANCY CHECK (CRC) operation to verify a program pattern VPP/WP# protection – Protects first or last block regardless of block protection settings Software protection – Volatile protection – Nonvolatile protection – Password protection Extended memory block – 128-word (256-byte) block for permanent, secure identification – Programmed or locked at the factory or by the customer JESD47-compliant – 100,000 (minimum) ERASE cycles per bloc...