Document
128Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR Features
Parallel NOR Flash Embedded Memory
MT28EW128ABA
Features
• Single-level cell (SLC) process technology • Density: 128Mb • Supply voltage
– VCC = 2.7–3.6V (program, erase, read) – VCCQ = 1.65 - VCC (I/O buffers) • Asynchronous random/page read – Page size: 16 words or 32 bytes – Page access: 20ns – Random access: 70ns (VCC = VCCQ = 2.7-3.6V) – Random access: 75ns (VCCQ = 1.65-VCC) • Buffer program (512-word program buffer) – 2.0 MB/s (TYP) when using full buffer program – 2.5 MB/s (TYP) when using accelerated buffer
program (VHH) • Word/Byte program: 25us per word (TYP) • Block erase (128KB): 0.2s (TYP) • Memory organization
– Uniform blocks: 128KB or 64KW each – x8/x16 data bus • Program/erase suspend and resume capability – Read from another block during a PROGRAM
SUSPEND operation – Read or program another block during an ERASE
SUSPEND operation • Unlock bypass, block erase, chip erase, and write to
buffer capability
• BLANK CHECK operation to verify an erased block • CYCLIC REDUNDANCY CHECK (CRC) operation to
verify a program pattern • VPP/WP# protection
– Protects first or last block regardless of block protection settings
• Software protection – Volatile protection – Nonvolatile protection – Password protection
• Extended memory block – 128-word (256-byte) block for permanent, secure identification – Programmed or locked at the factory or by the customer
• JESD47-compliant – 100,000 (minimum) ERASE cycles per block – Data retention: 20 years (TYP)
• Package – 56-pin TSOP, 14 x 20mm (JS) – 64-ball LBGA, 11 x 13mm (PC) – 56-ball VFBGA, 7 x 9mm (PN)
• RoHS-compliant, halogen-free packaging • Operating temperature
– Ambient: –40°C to +85°C
PDF: 09005aef85c59413 mt28e-qlhp-W128-ABA-S-IT.pdf - Rev. F 05/18 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
128Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR Features
Part Numbering Information
For available options, such as packages or high/low protection, or for further information, contact your Micron sales representative. Part numbers can be verified at www.micron.com. Feature and specification comparison by device type is available at www.micron.com/products. Contact the factory for devices not found.
Figure 1: Part Number Chart
MT 28E W 512 A B A 1 H JS - 0 S IT ES
Micron Technology
Part Family 28E = Embedded Parallel NOR
Voltage W = 2.7–3.6V VCC core
Density 128 = 128Mb 256 = 256Mb 512 = 512Mb 01G = 1Gb 02G = 2Gb
Stack A = Single die B = Two die
Device Generation B = 2nd generation
Die Revision A = Rev A
Configuration 1 = x8, x16
Production Status Blank = Production ES = Engineering sample
Operating Temperature IT = –40°C to +85°C
Special Options S = Standard
Security Features 0 = Standard default security 1 = OTP configurable
Package Codes JS = 56-pin TSOP, 14mm x 20mm PN = 56-ball VFBGA, 7mm x 9mm PC = 64-ball LBGA, 11mm x 13mm (All packages are lead-free, halogen-free, RoHS-compliant)
Block Structure H = High lock L = Low lock
PDF: 09005aef85c59413 mt28e-qlhp-W128-ABA-S-IT.pdf - Rev. F 05/18 EN
2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.
128Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR Features
Contents
Important Notes and Warnings ......................................................................................................................... 7 General Description ......................................................................................................................................... 8 Signal Assignments ........................................................................................................................................... 9 Signal Descriptions ......................................................................................................................................... 12 Memory Organization .................................................................................................................................... 14
Memory Configuration ............................................................................................................................... 14 Memory Map ............................................................................................................................................. 14 Bus Operations ............................................................................................................................................... 15 Read ..........................................................................................................................................................