Alterable E2PROM. X28C256 Datasheet

X28C256 Datasheet PDF, Equivalent


Part Number

X28C256

Description

32K x 8-Bit Alterable E2PROM

Manufacture

Xicor

Total Page 26 Pages
PDF Download
Download X28C256 Datasheet


X28C256 Datasheet
X28C256
256K
X28C256
5 Volt, Byte Alterable E2PROM
32K x 8 Bit
FEATURES
Access Time: 150ns
Simple Byte and Page Write
— Single 5V Supply
—No External High Voltages or VPP Control
Circuits
— Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS:
—Active: 60mA
—Standby: 200µA
Software Data Protection
— Protects Data Against System Level
Inadvertent Writes
High Speed Page Write Capability
Highly Reliable Direct WriteCell
— Endurance: 100,000 Write Cycles
— Data Retention: 100 Years
Early End of Write Detection
DATA Polling
—Toggle Bit Polling
PIN CONFIGURATION
DESCRIPTION
The X28C256 is an 32K x 8 E2PROM, fabricated with
Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28C256 is a 5V only device. The
X28C256 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard RAMs.
The X28C256 supports a 64-byte page write operation,
effectively providing a 78µs/byte write cycle and en-
abling the entire memory to be typically written in less
than 2.5 seconds. The X28C256 also features DATA
and Toggle Bit Polling, a system software support
scheme used to indicate the early completion of a write
cycle. In addition, the X28C256 includes a user-optional
software data protection mode that further enhances
Xicor’s hardware write protect capability.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
PLASTIC DIP
CERDIP
FLAT PACK
SOIC
LCC
PLCC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
X28C256
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
3855 FHD F02
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 A11
A3 8
A2 9
X28C256
26 NC
25 OE
A1 10
24 A10
A0 11
23 CE
NC 12
22 I/O7
I/O0
13 21
14 15 16 17 18 19 20
I/O6
3855 FHD F03
A2
A1
A0
I/O0
I/O1
I/O2
NC
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP
X28C256
32 A3
31 A4
30 A5
29 A6
28 A7
27 A12
26 A14
25 NC
24 VCC
23 NC
22 WE
21 A13
20 A8
19 A9
18 A11
17 OE
3855 ILL F23
© Xicor, Inc. 1991, 1995 Patents Pending
3855-2.0 8/19/98 T3/C0/D0 RZ
1 Characteristics subject to change without notice

X28C256 Datasheet
X28C256
PIN DESCRIPTIONS
Addresses (A0–A14)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28C256 through the
I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C256.
FUNCTIONAL DIAGRAM
PIN NAMES
Symbol
A0–A14
I/O0–I/O7
WE
CE
OE
VCC
VSS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
3855 PGM T01
PIN CONFIGURATION
PGA
I/O1 I/O2 I/O3 I/O5 I/O6
12 13 15 17 18
I/O0 A0
VSS I/O4 I/O7
11 10 14 16 19
A1 A2
98
CE A10
20 21
X28C256
A3 A4
OE A11
76
22 23
A5 A12 VCC A9 A8
5 2 28 24 25
A6 A7 A14 WE A13
4 3 1 27 26
3855 FHD F04
BOTTOM VIEW
A0–A14
ADDRESS
INPUTS
X BUFFERS
LATCHES AND
DECODER
Y BUFFERS
LATCHES AND
DECODER
256K-BIT
E2PROM
ARRAY
I/O BUFFERS
AND LATCHES
CE
OE
WE
VCC
VSS
CONTROL
LOGIC AND
TIMING
I/O0–I/O7
DATA INPUTS/OUTPUTS
3855 FHD F01
2


Features Datasheet pdf X28C256 256K X28C256 5 Volt, Byte Alter able E2PROM 32K x 8 Bit FEATURES • Access Time: 150ns • Simple Byte and Page Write — Single 5V Supply —No E xternal High Voltages or VPP Control Ci rcuits — Self-Timed —No Erase Befor e Write —No Complex Programming Algor ithms —No Overerase Problem • Low P ower CMOS: —Active: 60mA —Standby: 200µA • Software Data Protection — Protects Data Against System Level Ina dvertent Writes • High Speed Page Wri te Capability • Highly Reliable Direc t Write™ Cell — Endurance: 100,000 Write Cycles — Data Retention: 100 Ye ars • Early End of Write Detection DATA Polling —Toggle Bit Polling PI N CONFIGURATION DESCRIPTION The X28C25 6 is an 32K x 8 E2PROM, fabricated with Xicor’s proprietary, high performanc e, floating gate CMOS technology. Like all Xicor programmable nonvolatile memo ries the X28C256 is a 5V only device. T he X28C256 features the JEDEC approved pinout for bytewide memories, compatible with industry standard.
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