7 This specification applies to the period required for the PLL to relock after changing the MFD frequency
control bits in the synthesizer control register (SYNCR).
8 Assuming a reference is available at power up, lock time is measured from the time VDD and VDDSYN are
valid to RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the
crystal start up time must be added to the PLL lock time to determine the total start-up time.
9 tlpll = (64 * 4 * 5 + 5 × τ) × Tref, where Tref = 1/Fref_crystal = 1/Fref_ext = 1/Fref_1:1, and
τ = 1.57x10-6 × 2(MFD + 2).
10 PLL is operating in 1:1 PLL mode.
11 Jitter is the average deviation from the programmed frequency measured over the specified interval at
maximum fsys/2. Measurements are made with the device powered by filtered supplies and clocked by a
stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in
crystal oscillator frequency increase the Cjitter percentage for a given interval.
12 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of
13 Modulation percentage applies over an interval of 10μs, or equivalently the modulation rate is 100KHz.
14 Modulation rate selected must not result in fsys/2 value greater than the fsys/2 maximum specified value.
Modulation range determined by hardware design.
15 fsys/2 = fico / (2 * 2RFD)
7.5 External Interface Timing Characteristics
Table 11 lists processor bus input timings.
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the CLKOUT output.
All other timing relationships can be derived from these values.
Table 11. Processor Bus Input Timing Specifications
Symbol Min Max Unit
freq System bus frequency
B0 CLKOUT period
B1a Control input valid to CLKOUT high2
B1b BKPT valid to CLKOUT high3
B2a CLKOUT high to control inputs invalid2
B2b CLKOUT high to asynchronous control input BKPT invalid3
50 75 MHz
— 1/75 ns
9 — ns
tBKVCH 9 — ns
0 — ns
tBKNCH 0 — ns
B4 Data input (D[31:0]) valid to CLKOUT high
tDIVCH 4 —
B5 CLKOUT high to data input (D[31:0]) invalid
1 Timing specifications are tested using full drive strength pad configurations in a 50ohm transmission line
2 TEA and TA pins are being referred to as control inputs.
3 Refer to figure A-19.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 4
28 Freescale Semiconductor