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MT49H8M32 Dataheets PDF



Part Number MT49H8M32
Manufacturers Micron
Logo Micron
Description 1 Meg x 32 x 8 Banks Reduced Latency DRAM
Datasheet MT49H8M32 DatasheetMT49H8M32 Datasheet (PDF)

256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM Features Reduced Latency DRAM (RLDRAM®) MT49H8M32 – 1 Meg x 32 x 8 Banks MT49H16M16 – 2 Meg x 16 x 8 Banks For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/dram/rldram/ Features • Organization: 8 Meg x 32, 16 Meg x 16 in 8 banks • Cyclic bank addressing for maximum data bandwidth • Non multiplexed addresses • Non interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR • Up to 600 M.

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256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM Features Reduced Latency DRAM (RLDRAM®) MT49H8M32 – 1 Meg x 32 x 8 Banks MT49H16M16 – 2 Meg x 16 x 8 Banks For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/dram/rldram/ Features • Organization: 8 Meg x 32, 16 Meg x 16 in 8 banks • Cyclic bank addressing for maximum data bandwidth • Non multiplexed addresses • Non interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR • Up to 600 Mb/sec/pin data rate • Programmable READ latency (RL) of 5-6 • Data valid signal (DVLD) activated as read data is available • Data mask signals (DM0/DM1) to mask first and • second part of write data burst • IEEE 1149.1 compliant JTAG boundary scan • 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O • Pseudo-HSTL 1.8V I/O Supply • Internal auto precharge • Refresh requirements: 32ms at 95°C case temperature (8K refresh for each bank, 64K refresh command must be issued in tota.


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