3.3V 64K x 16 CMOS SRAM
September 2006 Advance Information
AS7C31026C
®
3.3 V 64K X 16 CMOS SRAM
Features • Industrial (-40o to 85oC) tempera...
Description
September 2006 Advance Information
AS7C31026C
®
3.3 V 64K X 16 CMOS SRAM
Features Industrial (-40o to 85oC) temperature Organization: 65,536 words × 16 bits Center power and ground pins for low noise
High speed - 12 ns address access time - 6 ns output enable access time
Low power consumption via chip deselect Upper and Lower byte pin Easy memory expansion with CE, OE inputs
TTL-compatible, three-state I/O
JEDEC standard packaging - 44-pin 400 mil SOJ - 44-pin TSOP 2-400 - 48-ball 7 × 7 mm BGA
ESD protection ? 2000 volts
Logic block diagram
Address decoder
A0
A1 A2 A3 A4 A5 A6 A7
I/O0–I/O7 I/O8–I/O15
bIu/Offer
WE
65,536 × 16 Array
VCC GND
Control circuit Address decoder
A8 A9 A10 A11 A12 A13 A14 A15
UB OE LB
CE
Pin arrangement
44-Pin SOJ (400 mil), TSOP 2
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
AS7C31026C
44 A5 43 A...
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