CMOS Gate Array
Core Logic
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$0,+* PLFURQ &026 *DWH $UUD\
Description AN3x is a family of AND-NOR circuits consisting of on...
Description
Core Logic
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®
$0,+* PLFURQ &026 *DWH $UUD\
Description AN3x is a family of AND-NOR circuits consisting of one 2-input AND gate into a 3-input NOR gate.
Logic Symbol
Truth Table
A
AN3x
A B CDQ
LXL LH B
Q XLLLH
C HHXX L
D XXHXL
XXXHL
HDL Syntax Verilog .................... AN3x inst_name (Q, A, B, C, D); VHDL...................... inst_name: AN3x port map (Q, A, B, C, D);
Pin Loading
Pin Name
A B C D
AN31 1.0 1.0 1.0 1.0
Equivalent Loads
AN32
AN34
1.0 1.0
1.0 1.0
1.0 1.0
1.0 1.0
AN36 2.1 2.1 2.1 2.1
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
AN31
2.0
TBD
2.5
AN32
4.0
TBD
9.1
AN34
4.0
TBD
8.0
AN36
8.0
TBD
16.6
a. See page 2-15 for power equation.
3-11
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$0,+* PLFURQ &026 *DWH $UUD\
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
AN31
Number of Equivalent Loads
From: Any Input To: Q
tPLH tPHL
Number of Equivalent ...
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