CMOS Gate Array
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$0,+* PLFURQ &026 *DWH $UUD\
Description AN7x is a family of AND-NOR circuits consisting of one 3-input AN...
Description
$1[
®
$0,+* PLFURQ &026 *DWH $UUD\
Description AN7x is a family of AND-NOR circuits consisting of one 3-input AND gate into a 3-input NOR gate.
Logic Symbol
Truth Table
A
AN7x
ABCDEQ
B HHHXX L C
Q XXXHXL
D XXXXHL
E
All other combinations
H
Core Logic
HDL Syntax Verilog .................... AN7x inst_name (Q, A, B, C, D, E); VHDL...................... inst_name: AN7x port map (Q, A, B, C, D, E);
Pin Loading
Pin Name
A B C D E
AN72 1.0 1.0 1.0 1.0 1.0
Equivalent Loads AN74 1.0 1.0 1.0 1.0 1.0
AN76 2.1 2.1 2.1 2.1 2.1
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
AN72 AN74 AN76
5.0 5.0 10.0
TBD TBD TBD
9.9 9.2 16.8
a. See page 2-15 for power equation.
3-19
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$0,+* PLFURQ &026 *DWH $UUD\
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Number of Equivalent Loads
1
4
AN72
From: Any Input To: Q
tPLH tPHL
0.47 0.50
0.58 0.62
Number ...
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