Gate Array. DF002 Datasheet

DF002 Array. Datasheet pdf. Equivalent

Part DF002
Description CMOS Gate Array
Feature Core Logic ')[ ® $0,+*  PLFURQ &026 *DWH $UUD Description DF00x is a family of static, mast.
Manufacture AMI
Datasheet
Download DF002 Datasheet



DF002
')[
®
$0,+*  PLFURQ &026 *DWH $UUD\
Description
DF00x is a family of static, master-slave D flip-flops without SET or RESET. Output is unbuffered and changes state on
the rising edge of the clock.
Logic Symbol
Truth Table
DF00x
DQ
C
DCQ
HH
LL
X L NC
NC = No Change
HDL Syntax
Verilog .................... DF00x inst_name (Q, C, D);
VHDL...................... inst_name: DF00x port map (Q, C, D);
Pin Loading
Pin Name
D
C
Equivalent Loads
DF001
DF002
1.0 1.0
1.0 1.0
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
DF001
6.0
TBD
14.0
DF002
7.0
TBD
15.7
a. See page 2-15 for power equation.
3-49



DF002
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$0,+*  PLFURQ &026 *DWH $UUD\
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Number of Equivalent Loads
1
4
DF001
From: C
To: Q
tPLH
tPHL
0.66
0.56
0.75
0.67
Number of Equivalent Loads
1
8
DF002
From: C
To: Q
tPLH
tPHL
0.68
0.58
0.78
0.76
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
Timing Constraints
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
From Delay (ns) To Parameter
Cell
DF001
Min C Width
Min C Width
Min D Setup
Min D Hold
High
Low
tw
tw
tsu
th
0.65
0.69
0.42
0.17
DF002
0.67
0.69
0.42
0.17
Logic Schematic
CB
CN
8
0.86
0.80
15
0.89
0.88
13
1.00
0.96
22
0.99
0.98
D
CN
CN
CB
CB
®
17 (max)
1.12
1.08
30 (max)
1.10
1.09
Q
CB
C CB
CN
CN
3-50







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