DF011

Core Logic ') ® $0,+*  PLFURQ &026 *DWH $UUD\ Description DF011 is a static, master-slave D flip-flop. RESET is asynchronous and active low. Output is unbuffered and changes state on the rising edge of the clock. Logic Symbol Truth Table Pin Loading DF011 DQ C R RN D C Q LXXL HL ↑L HH ↑H H X L NC NC = No Change Equivalent Load D 1.0 C 1.0 RN 1.0 Equivalent Gates ................ 8.0 HDL Syntax Verilog .................... DF011 inst_name (Q, C, D, RN); VHDL...................... inst_name: DF011 port map (Q, C, D, RN); Size And Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 17.8 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process From Delay (ns) To Parameter 1 Number of Equivalent Loads 258 C Q tPLH tPHL 0.72 0.57 0.78 0.62 RN Q tPHL 0.31 0.35 Delay will vary with input conditions. See page 2-17 for interconnect estimates. 0.94 0.72 0.45 1.09 0.81 0.5...