DF1F6

Core Logic '))[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Description DF1Fx is a family of static, master-slave D flip-flops without SET or RESET. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol Truth Table DF1Fx DQ C Q D C Q QN XX L H L ↑LH H↑HL X L NC NC NC = No Change HDL Syntax Verilog .................... DF1Fx inst_name (Q, QN, C, D); VHDL...................... inst_name: DF1Fx port map (Q, QN, C, D) Pin Loading Pin Name D C DF1F1 1.0 1.0 Equivalent Loads DF1F2 DF1F4 1.0 1.0 1.0 1.0 DF1F6 1.0 1.0 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) DF1F1 7.0 TBD 17.4 DF1F2 8.0 TBD 20.7 DF1F4 11.0 TBD 30.7 DF1F6 14.0 TBD 38.9 a. See page 2-15 for power equation. 3-67 Core Logic '))[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent Loads 1 DF1F1 F...