Core Logic
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Description
DF20x is a family of static, master-slave, multiplexed scan D flip-flops without SET or RESET. Output is unbuffered and changes state on the rising edge of the clock.
Logic Symbol
Truth Table
DF20x
DQ C SD SE
C D SD SE Q ↑HX LH ↑LXLL ↑ XHHH ↑XLHL L X X X NC
NC = No Change
HDL Syntax Verilog DF20x inst_name (Q, C, D, SD, SE); VHDL.. inst_name: DF20x port map (Q, C, D, SD, SE);
Pin L.