DF211

Core Logic ') ® $0,+*  PLFURQ &026 *DWH $UUD\ Description DF211 is a static, master-slave, multiplexed scan D flip-flop. RESET is asynchronous and active low. Output is unbuffered and changes state on the rising edge of the clock. Logic Symbol DF211 D C SD SE R Q Truth Table C ↑ ↑ ↑ ↑ X L D RN SD SE Q HHX L L HX L XHHH XHLH XLXX XHXX NC = No Change H L H L L NC Pin Loading Equivalent Load C 1.0 D 1.0 RN 1.0 SD 1.0 SE 2.1 Equivalent Gates ................ 11.0 HDL Syntax Verilog .................... DF211 inst_name (Q, C, D, RN, SD, SE); VHDL...................... inst_name: DF211 port map (Q, C, D, RN, SD, SE); Size And Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 22.3 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process From Delay (ns) To Parameter 1 Number of Equivalent Loads 258 C Q tPLH tPHL 0.74 0.58 0.79 0.63 RN Q tPHL 0.32 0.36 Delay will...