Core Logic
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Description DL65x is a family of transparent, buffered D latches with active low gate transparency. SET is active low.
Logic Symbol
Truth Table
DL65x
DSQ G
Q
SN GN D Q QN L XXH L H H X NC NC HL L LH H L HH L
NC = No Change
HDL Syntax Verilog DL65x inst_name (Q, QN, D, GN, SN); VHDL.. inst_name: DL65x port map (Q, QN, D, GN, SN);
Pin Loading
Pin Name
D GN SN
DL651 1.0 1.0 1.0
Equivalent Loads
D.