JK022

Core Logic -.[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Description JK02x is a family of static, master-slave JK flip-flops. SET is asynchronous and active low. Output is unbuffered and changes state on the rising edge of the clock. Logic Symbol JK02x J SQ C K Truth Table SN J K C Q(n+1) LXXX H H L L ↑ NC HLH↑ L HHL ↑ H H H H ↑ Q(n) NC = No Change HDL Syntax Verilog .................... JK02x inst_name (Q, C, J, K, SN); VHDL...................... inst_name: JK02x port map (Q, C, J, K, SN); Pin Loading Pin Name J K C SN Equivalent Loads JK021 JK022 1.0 1.0 1.0 1.0 1.0 1.0 2.1 3.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) JK021 11.0 TBD 22.3 JK022 11.0 TBD 24.3 a. See page 2-15 for power equation. 3-140 Core Logic -.[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent Loads ...