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Core Logic
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®
$0,+* PLFURQ &026 *DWH $UUD\
Description
JK031 is a static, master-slave JK flip-flop. SET and RESET are asynchronous and active low. Output is unbuffered and changes state on the rising edge of the clock.
Logic Symbol
JK031
J SQ C K
R
Truth Table RN SN J K L LXX LHXX HLXX HHL L HH L H HHH L HHHH IL = Illegal
C Q(n+1) X IL XL XH ↑ NC ↑L ↑H ↑ Q(n) NC = No Change
Pin Loading
Equivalent Load
J 1.0 K 1.0 C 1.0 SN 2.1 RN 2.2
Equivalent Gates ................ 12.0
HDL Syntax Verilog .................... JK031 inst_name (Q, C, J, K, RN, SN); VHDL...................... inst_name: JK031 port map (Q, C, J, K, RN, SN);
Size And Power Characteristics
Parameter
Static IDD (TJ = 85°C) EQLpd
See page 2-15 for power equation.
Value TBD 26.2
Units nA
Eq-load
Propagation Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
From Delay (ns) To Parameter
1
Number of Equivalent Loads 258
C
Q
tPLH tPHL
0.76 0.80
0.80 0.87
RN
Q tPHL
0.94
0.99
S.