JK124

-.[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Description JK12x is a family of static, master-slave JK flip-flops. SET and RESET are asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol JK12x J SQ C K Q R Truth Table RN SN J K L L XX LHXX HLXX HHL L HH L H HHH L HHHH IL = Illegal C Q(n+1) QN(n+1) X IL IL XL H XH L ↑ NC NC ↑L H ↑H L ↑ QN(n) Q(n) NC = No Change Core Logic HDL Syntax Verilog .................... JK12x inst_name (Q, QN, C, J, K, RN, SN); VHDL...................... inst_name: JK12x port map (Q, QN, C, J, K, RN, SN); Pin Loading Pin Name J K C SN RN JK121 1.0 1.0 1.1 2.1 2.2 Equivalent Loads JK122 JK124 1.0 1.0 1.0 1.1 1.0 1.0 2.1 2.1 1.1 1.1 JK126 1.0 1.0 1.0 2.1 1.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) JK121 13.0 TBD 29.9 JK122 15.0 TBD 37.0 JK124 17.0 TBD 42.7 3-145 Core Logi...