Core Logic
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Description MXI2x is a family of inverting two-to-one digital multiplexers.
Logic Symbol
Truth Table
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MXI2x S
I0 Q I1
S I0 I1 QN L LXH L HX L HX L H HXHL
HDL Syntax Verilog MXI2x inst_name (QN, I0, I1, S); VHDL.. inst_name: MXI2x port map (QN, I0, I1, S);
Pin Loading
Pin Name
I0 I1 S
MXI21 1.0 1.0 2.2
Equivalent Loads
MXI22
MXI24
1.0 1.0
1.0 1.0
2.2 2.1
MXI26 1.0 1.0 2.1
Size And Power .