System Controller. NS32FV100-20 Datasheet

NS32FV100-20 Controller. Datasheet pdf. Equivalent

NS32FV100-20 Datasheet
Recommendation NS32FV100-20 Datasheet
Part NS32FV100-20
Description System Controller
Feature NS32FV100-20; NS32FX100-15 NS32FX100-20 NS32FV100-20 NS32FV100-25 NS32FX200-20 NS32FX200-25 System Controller PRE.
Manufacture National Semiconductor
Datasheet
Download NS32FV100-20 Datasheet




National Semiconductor NS32FV100-20
PRELIMINARY
July 1992
NS32FX100-15 NS32FX100-20 NS32FV100-20
NS32FV100-25 NS32FX200-20 NS32FX200-25
System Controller
General Description
The NS32FX200 NS32FV100 and NS32FX100 are highly
integrated system chips designed for a FAX system based
on National Semiconductor’s embedded processors
NS32FX161 NS32FV16 or NS32FX164 The NS32FX100 is
the common core for all three system chips The
NS32FV100 and NS32FX200 offer additional functions
Throughout this document references to the NS32FX100
also apply to both the NS32FV100 and the NS32FX200
Specific NS32FV100 or NS32FX200 features are explicitly
indicated
The NS32FX200 NS32FV100 and NS32FX100 feature an
interface to devices like stepper motors printers and scan-
ners a Sigma-Delta CODEC an elapsed-time counter a
DMA controller an interrupt controller and a UART
The NS32FX200 is optimized for high-end FAX applications
such as plain-paper FAX and multifunctional peripherals
The NS32FX100 is optimized for low-cost FAX applica-
tions The NS32FV100 is optimized for thermal paper FAX
machines with Digital Answering Machine support
Features
Y Direct interface to the NS32FX161 NS32FV16 and
NS32FX164 embedded processors
Y Supports a variety of Contact Image Sensor (CIS) and
Charge Coupled Device (CCD) scanners
Y Direct interface to a variety of Thermal Print Head
(TPH) printers Bitmap shifter and DMA channels facili-
tate the connection of other types of printers
Y Supports two stepper motors
Y Direct interface to ROM and SRAM The NS32FX200
and NS32FV100 in addition interface to DRAM
devices
Y Programmable wait state generator
Y Demultiplexed address and data buses
Y Multiplexed DRAM address bus (NS32FX200 and
NS32FV100)
Y Supports 3V freeze mode by maintaining only elapsed
time counter
Y Control of power consumption by disabling inactive
modules and reducing the clock frequency
Y Operating frequency
Normal mode 19 6608 MHz 24 576 MHz in steps
of 1 2288 MHz (NS32FX200)
Normal mode 19 6608 MHz 24 576 MHz in steps
of 1 2288 MHz (NS32FV100)
Normal mode 14 7456 MHz 19 6608 MHz in steps
of 1 2288 MHz (NS32FX100)
Power Save mode Normal mode frequency divided
by sixteen
Y On-Chip full duplex Sigma-Delta CODEC with
Total harmonic distortion better than b70 dB
Programmable hybrid balance filter
Programmable reception and transmission filters
Programmable gain control
Y On-Chip Interrupt Control Unit with
16 interrupt sources
Programmable triggering mode
Y On-Chip counters WATCHDOGTM UART
MICROWIRETM System Clock Generator and I O
ports
Y On-Chip DMA controller (NS32FX200 four channels
NS32FX100 NS32FV100 three channels)
Y Up to 37 on-chip general purpose I O pins expandable
externally
Y Flexible allocation of I O and modules’ pins
Y 132-pin JEDEC PQFP package
FIGURE 1-1 A FAX Controller Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
MICROWIRETM and WATCHDOGTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL EE11331
TL EE 11331 – 1
RRD-B30M105 Printed in U S A



National Semiconductor NS32FV100-20
Table of Contents
1 0 FAX SYSTEM CONFIGURATION
6
1 1 Block Diagram Description
6
1 2 Module Diagram
7
1 2 1 Bus and Memory Controller (BMC)
8
1 2 2 Timing Control Unit (TCU)
8
1 2 3 Sigma-Delta CODEC (SDC)
8
1 2 4 Scanner Controller (SCANC)
8
1 2 5 Printer Controller (PRNTC)
8
1 2 6 DMA Controller (DMAC)
8
1 2 7 Universal Asynchronous Receiver-Transmitter
(UART)
8
1 2 8 MICROWIRE (MWIRE)
8
1 2 9 Interrupt Control Unit (ICU)
8
1 2 10 Ports
8
1 3 Operation Modes
8
1 3 1 Functionality
9
2 0 ARCHITECTURE
2 1 MCFG Module Configuration Register
2 2 Timing Control Unit (TCU)
2 2 1 Features
2 2 2 Operation
2 2 2 1 External Clocks
2 2 2 2 Internal Clocks
2 2 3 Registers
2 2 3 1 Usage Recommendations
2 3 Sigma-Delta CODEC (SDC)
2 3 1 Features
2 3 2 Operation
2 3 2 1 Block Diagram
2 3 2 2 On-Chip Digital Blocks
2 3 3 Programmable Functions
2 3 3 1 Sigma-Delta ON OFF
2 3 4 Off-Chip Analog Circuits
2 3 4 1 Analog Transmitter
2 3 4 2 Analog Receiver
2 3 5 Registers
2 3 6 Usage Recommendations
2 4 Scanner Controller (SCANC)
2 4 1 Features
2 4 2 Operation
2 4 2 1 Scanner Signals Generator Block
2 4 2 2 Scanner Period Pulse (SPP)
Generation
2 4 2 3 Video Handling Block
2 4 2 4 Threshold DAC (Dithering and
Automatic Background Control)
2 4 2 5 Stepper Motor Control Block
10
10
10
10
10
11
11
12
13
13
13
13
13
15
15
15
15
17
17
17
18
18
18
18
19
20
21
22
23
2 0 ARCHITECTURE (Continued)
2 4 3 Registers
2 4 4 Usage Recommendations
23
24
2 5 Printer Controller (PRNTC)
25
2 5 1 Features
2 5 2 Operation
2 5 2 1 Printer Bitmap Shifter Block
2 5 2 2 Thermal Print-Head Control Block
2 5 3 Registers
2 5 4 Usage Recommendations
25
25
25
25
28
28
2 6 Direct Memory Access Controller (DMAC)
29
2 6 1 Features
2 6 2 Description
2 6 2 1 A General DMA Channel
2 6 2 2 Transfer Types
2 6 2 3 Operation Modes
2 6 3 Detailed Operation Flow
2 6 4 NS32FX200 DMA Channels
2 6 5 Registers
2 6 6 Usage Recommendations
2 6 7 DMAC Bus Cycles
29
29
29
29
29
29
30
30
32
32
2 7 Universal Asynchronous Receiver-Transmitter
(UART)
36
2 7 1 Features
2 7 2 Operation
2 7 3 Registers
2 7 4 Usage Recommendations
36
36
37
38
2 8 MICROWIRE (MWIRE)
38
2 8 1 Features
2 8 2 Operation
2 8 3 Registers
2 8 4 Usage Recommendations
38
38
38
40
2 9 Interrupt Control Unit (ICU)
40
2 9 1 Features
2 9 2 Operation
2 9 3 Registers
2 9 4 Usage Recommendations
40
40
41
41
2 10 Ports Module
41
2 10 1 Features
41
2 10 2 Operation
41
2 10 2 1 General Purpose Input Output
Ports
41
2 10 2 2 External Output Port Extension 43
2 10 2 3 Stepper Motors Output Ports 43
2 10 3 Registers
43
2 10 4 Usage Recommendations
45
2



National Semiconductor NS32FV100-20
Table of Contents (Continued)
2 0 ARCHITECTURE (Continued)
2 11 Bus and Memory Controller (BMC)
45
2 11 1 Features
45
2 11 2 Operation
45
2 11 2 1 Zones 0 1 (ROM and SRAM)
Transactions
46
2 11 2 2 Zone 2 (Dynamic Memory)
Transactions (NS32FX200 and
NS32FV100 only)
46
2 11 2 3 Zone 3 (I O) Transactions
47
2 11 2 4 Operation in Freeze Mode
47
2 11 2 5 On-Chip Registers Access
47
2 11 3 Registers
2 11 4 Usage Recommendations
47
48
2 12 Register Summary
48
2 12 1 NS32FX100 Registers Access Method 48
2 12 2 NS32FX200 NS32FV100 and NS32FX100
Registers
48
3 0 SYSTEM INTERFACE
3 1 Power and Grounding
3 2 Clocks and Traps Connectivity
53
53
53
3 0 SYSTEM INTERFACE (Continued)
3 3 Control of Power Consumption
3 4 Bus Cycles
53
54
4 0 DEVICE SPECIFICATIONS
62
4 1 NS32FX100 Pin Descriptions
4 1 1 Supplies
4 1 2 Input Signals
4 1 3 Output Signals
4 1 4 Input Output Signals
62
62
62
63
64
4 2 Output Signal Levels
4 2 1 Freeze Mode Output Signals
4 2 2 Reset Power Restore Output Signals
64
65
65
4 3 Absolute Maximum Ratings
67
4 4 Electrical Characteristics
67
4 5 Analog Electrical Characteristics
69
4 6 Switching Characteristics
70
4 6 1 Definitions
70
4 6 2 Timing Tables
71
4 6 2 1 Output Signals Internal Propagation
Delays
71
4 6 2 2 Input Signal Requirements
76
APPENDIX A CODEC TRANSMISSION
PERFORMANCE
92
3







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