Document
Core Logic
21[
®
$0,+* PLFURQ &026 *DWH $UUD\
Description ON7x is a family of OR-NAND circuits consisting of one 3-input OR gate into a 3-input NAND gate.
Logic Symbol
A B C
D E
Truth Table
ON7x
Q
ABCDE L L LXX XXXLX XXXXL
All other combinations
Q H H H L
Pin Loading Equivalent Load
A 1.0 B 1.0 C 1.0 D 1.0 E 1.0
HDL Syntax Verilog .................... ON7x inst_name (Q, A, B, C, D, E); VHDL...................... inst_name: ON7x port map (Q, A, B, C, D, E);
Pin Loading
Pin Name
A B C D E
ON72 1.0 1.0 1.0 1.0 1.0
Equivalent Loads ON74 1.0 1.0 1.0 1.0 1.0
ON76 2.1 2.1 2.1 2.1 2.1
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
ON72
5.0
TBD
10.3
ON74
5.0
TBD
7.4
ON76
10.0
TBD
18.1
a. See page 2-15 for power equation.
3-193
21[
®
$0,+* PLFURQ &026 *DWH $UUD\
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Number of Equivalent Loads
1
4
.