CMOS Gate Array
Core Logic
25[
®
$0,+* PLFURQ &026 *DWH $UUD\
Description OR4x is a family of 4-input gate which performs the l...
Description
Core Logic
25[
®
$0,+* PLFURQ &026 *DWH $UUD\
Description OR4x is a family of 4-input gate which performs the logical OR function.
Logic Symbol
Truth Table
OR4x
A
B C
Q
D
A
B C
Q
D
A B CDQ LLLLL HXXXH XHXXH XXHXH XXXHH
HDL Syntax Verilog .................... OR4x inst_name (Q, A, B, C, D); VHDL...................... inst_name: OR4x port map (Q, A, B, C, D);
Pin Loading
Pin Name
A B C D
OR41 1.0 1.0 1.0 1.0
Equivalent Loads
OR42
OR44
1.0 3.2
1.0 3.2
1.0 3.2
1.0 3.2
OR46 3.1 3.1 3.1 3.1
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
OR41
3.0
TBD
4.8
OR42
4.0
TBD
7.8
OR44
8.0
TBD
12.3
OR46
9.0
TBD
16.8
a. See page 2-15 for power equation.
3-215
25[
$0,+* PLFURQ &026 *DWH $UUD\
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
OR41
Number of Equivalent Loads
From: Any Input To: Q
tPLH tPHL
Number of Equivalent Loads
1
0....
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