SLF012

Core Logic 6/)[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Description SLF01x is a family of static, master-slave, multiplexed scan latch, D flip-flops. When SCE is low it is a D flip-flop with the output buffered and changes state on the rising edge of the clock. When SCE is high it is a D latch that is transparent when C is low. RESET is asynchronous and active low. Logic Symbol SLF01x DQ C SD SE SCE R Truth Table RN C D SD SE SCE Q H↑HXL LH H↑LXL L L H ↑ XHH L H H↑XLHL L H L X X X L NC HLHX LHH HL LXLHL HL XHHHH HL X LHHL H H X X X H NC LXXXXXL NC = No Change HDL Syntax Verilog .................... SLF01x inst_name (Q, C, D, RN, SCE, SD, SE); VHDL...................... inst_name: SLF01x port map (Q, C, D, RN, SCE, SD, SE); Pin Loading Pin Name C D RN SD SE SCE SLF011 1.0 1.0 1.1 1.0 2.2 2.2 Equivalent Loads SLF012 SLF014 1.0 1.0 1.0 1.0 1.1 1.1 1.0 1.0 2.2 2.2 2.2 2.2 SLF016 1.0 1.0 1.0 1.0 2.2 2.1 3-221 Core Logic 6/)[ $0,+*  PLFURQ &026 *DWH $UUD\ ...