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IDCS3

CMOS Gate Array

Description

,'&6 ® $0,+* PLFURQ &026 *DWH $UUD\ Description IDCS3 is a non-inverting, CMOS-level Schmitt trigger input buffer piece with voltage hysteresis. Logic Symbol Truth Table Pin Loading IDCS3 QC P PADM D PADM QC LL HH Load PADM 4.90 pF HDL Syntax Verilog .................... IDCS3 inst_name (QC, PADM); VHDL...................... inst_name: IDCS3 p...

AMI

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