IDCX3

,'&;[ $0,+*  PLFURQ &026 *DWH $UUD\ Description IDCXx is a family of non-inverting, CMOS-level input buffer pieces. Logic Symbol Truth Table IDCXx QC P PADM D PADM QC LL HH HDL Syntax Verilog .................... IDCXx inst_name (QC, PADM); VHDL...................... inst_name: IDCXx port map (QC, PADM); Pin Loading Pin Name PADM (pF) Load IDCX3 IDCX6 4.90 4.90 Power Characteristics Cell Equivalent Gates IDCX3 IDCX6 0.0 0.0 a. See page 2-15 for power equation. Power Characteristicsa Static IDD (TJ = 85°C) (nA) TBD EQLpd (Eq-load) 10.4 TBD 18.1 Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent Loads 1 IDCX3 From: PADM To: QC tPLH tPHL 0.63 0.63 Number of Equivalent Loads 1 IDCX6 From: PADM To: QC tPLH tPHL 0.60 0.61 Delay will vary with input conditions. See page 2-17 for interconnect estimates. 11 0.79 0.76 11 0.69 0.66 22 0.90 0.88 22 0.75 0.73 ® 32 1.00 0.98 32 0.80 0.81 43 (max) 1.09 1.07...