IDQC0

,'4& ® $0,+*  PLFURQ &026 *DWH $UUD\ Description IDQC0 is a non-buffered, resistive crystal oscillator input receiver piece with ESD protection. Logic Symbol Truth Table Pin Loading IDQC0 QC P PADM D PADM QO LL HH PADM Load 4.90 pF HDL Syntax Verilog .................... IDQC0 inst_name (QO, PADM); VHDL...................... inst_name: IDQC0 port map (QO, PADM); Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 2.1 Units nA Eq-load Design Notes: The IDQC0 cell is for backward compatibility with existing oscillator methodologies. Pad Logic 4-6 ...