ODCSIP08 Datasheet PDF | AMI





(PDF) ODCSIP08 Datasheet PDF

Part Number ODCSIP08
Description CMOS Gate Array
Manufacture AMI
Total Page 2 Pages
PDF Download Download ODCSIP08 Datasheet PDF

Features: 2'&6,3[[ ® $0,+*  PLFURQ &026 *DWH $UUD Description ODCSIPxx is a family of 4 to 8 mA, inverting, CMOS-level ou tput buffer pieces with P-channel open- drains (pull-up) and controlled slew ra te outputs. Logic Symbol Truth Table ODCSIPxx A SL PADM A PADM LH HZ Z = H igh Impedance HDL Syntax Verilog ..... ............... ODCSIPxx inst_name (PAD M, A); VHDL...................... inst_ name: ODCSIPxx port map (PADM, A); Pin Loading Pin Name A (eq-load) PADM (pF ) ODCSIP04 4.1 4.94 Power Characteris tics Cell Output Drive (mA) ODCSIP04 4 ODCSIP08 8 ODCSIP12 12 a. See p age 2-15 for power equation. Load ODCS IP08 4.1 4.94 ODCSIP12 4.1 4.94 Power Characteristicsa Static IDD (TJ = 85 C) (nA) TBD EQLpd (Eq-load) 190.5 TB D 203.6 TBD 216.8 Pad Logic 4-15 2'&6,3[[ $0,+*  PLFURQ &026 *DWH $ UUD Propagation Delays (ns) Conditions : TJ = 25°C, VDD = 5.0V, Typical Proce ss ODCSIP04 Capacitive Load (pF) Fro m: A To: PADM tZH 15 2.64 ODCSIP08 Capacitive Load (pF) .

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ODCSIP08 datasheet
2'&6,3[[
®
$0,+*  PLFURQ &026 *DWH $UUD\
Description
ODCSIPxx is a family of 4 to 8 mA, inverting, CMOS-level output buffer pieces with P-channel open-drains (pull-up) and
controlled slew rate outputs.
Logic Symbol
Truth Table
ODCSIPxx
A SL
PADM
A PADM
LH
HZ
Z = High Impedance
HDL Syntax
Verilog .................... ODCSIPxx inst_name (PADM, A);
VHDL...................... inst_name: ODCSIPxx port map (PADM, A);
Pin Loading
Pin Name
A (eq-load)
PADM (pF)
ODCSIP04
4.1
4.94
Power Characteristics
Cell Output Drive (mA)
ODCSIP04
4
ODCSIP08
8
ODCSIP12
12
a. See page 2-15 for power equation.
Load
ODCSIP08
4.1
4.94
ODCSIP12
4.1
4.94
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
TBD
EQLpd (Eq-load)
190.5
TBD
203.6
TBD
216.8
4-15

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