ODCSXE12 Datasheet: CMOS Gate Array





ODCSXE12 CMOS Gate Array Datasheet

Part Number ODCSXE12
Description CMOS Gate Array
Manufacture AMI
Total Page 2 Pages
PDF Download Download ODCSXE12 Datasheet PDF

Features: 2'&6;([[ ® $0,+*  PLFURQ &026 *DWH $UUD Description ODCSXExx is a family of 4 to 16 mA, non-inverting, CMOS-lev el, tristate output buffer pieces with active low enables and controlled slew rate outputs. Logic Symbol Truth Tabl e ODCSXExx EN SL A PADM EN A PADM LL L LH H HX Z HDL Syntax Verilog . ................... ODCSXExx inst_name (PADM, A, EN); VHDL.................... .. inst_name: ODCSXExx port map (PADM, A, EN); Pin Loading Pin Name A (eq-lo ad) EN (eq-load) PADM (pF) ODCSXE04 2. 3 6.9 4.94 Power Characteristics Cell Output Drive (mA) ODCSXE04 4 ODCSXE 08 8 ODCSXE12 12 ODCSXE16 16 a. S ee page 2-15 for power equation. ODCSX E08 2.3 6.9 4.94 Load ODCSXE12 2.3 6. 9 4.94 ODCSXE16 2.3 6.9 4.94 Power Ch aracteristicsa Static IDD (TJ = 85°C) (nA) TBD EQLpd (Eq-load) 218.9 TBD 240.3 TBD 261.1 TBD 283.9 Pad Logi c 4-17 2'&6;([[ ® $0,+*  PLFUR Q &026 *DWH $UUD Propagation Delays (n s) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Capac.

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2'&6;([[
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$0,+*  PLFURQ &026 *DWH $UUD\
Description
ODCSXExx is a family of 4 to 16 mA, non-inverting, CMOS-level, tristate output buffer pieces with active low enables
and controlled slew rate outputs.
Logic Symbol
Truth Table
ODCSXExx
EN
SL
A
PADM
EN A PADM
LL
L
LH
H
HX
Z
HDL Syntax
Verilog .................... ODCSXExx inst_name (PADM, A, EN);
VHDL...................... inst_name: ODCSXExx port map (PADM, A, EN);
Pin Loading
Pin Name
A (eq-load)
EN (eq-load)
PADM (pF)
ODCSXE04
2.3
6.9
4.94
Power Characteristics
Cell Output Drive (mA)
ODCSXE04
4
ODCSXE08
8
ODCSXE12
12
ODCSXE16
16
a. See page 2-15 for power equation.
ODCSXE08
2.3
6.9
4.94
Load
ODCSXE12
2.3
6.9
4.94
ODCSXE16
2.3
6.9
4.94
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
TBD
EQLpd (Eq-load)
218.9
TBD
240.3
TBD
261.1
TBD
283.9
4-17

     






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