ODCSXX16 Array Datasheet

ODCSXX16 Datasheet, PDF, Equivalent


Part Number

ODCSXX16

Description

CMOS Gate Array

Manufacture

AMI

Total Page 2 Pages
Datasheet
Download ODCSXX16 Datasheet


ODCSXX16
2'&6;;[[
®
$0,+*  PLFURQ &026 *DWH $UUD\
Description
ODCSXXxx is a family of 4 to 24 mA, non-inverting, CMOS-level, output buffer pieces with controlled slew rate outputs.
Logic Symbol
Truth Table
ODCSXXxx
SL
A
PADM
A PADM
LL
HH
HDL Syntax
Verilog .................... ODCSXXxx inst_name (PADM, A);
VHDL...................... inst_name: ODCSXXxx port map (PADM, A);
Pin Loading
Pin Name
A (eq-load)
ODCSXX04
9.3
Power Characteristics
Cell Output Drive (mA)
ODCSXX04
4
ODCSXX08
8
ODCSXX12
12
ODCSXX16
16
ODCSXX24
24
a. See page 2-15 for power equation.
ODCSXX08
9.3
Load
ODCSXX12
9.3
ODCSXX16
9.3
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
TBD
EQLpd (Eq-load)
198.6
TBD
220.0
TBD
240.8
TBD
263.6
TBD
282.3
ODCSXX24
11.4
4-19

ODCSXX16
2'&6;;[[
$0,+*  PLFURQ &026 *DWH $UUD\
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Capacitive Load (pF)
15
ODCSXX04
From: A
tPLH
To: PADM tPHL
2.46
2.44
Capacitive Load (pF)
15
ODCSXX08
From: A
tPLH
To: PADM tPHL
1.50
1.64
Capacitive Load (pF)
15
ODCSXX12
From: A
tPLH
To: PADM tPHL
1.35
1.47
Capacitive Load (pF)
15
ODCSXX16
From: A
tPLH
To: PADM tPHL
1.29
1.44
Capacitive Load (pF)
15
ODCSXX24
From: A
tPLH
To: PADM tPHL
1.31
1.12
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
50
6.09
6.13
50
3.36
3.50
50
2.58
2.58
50
2.19
2.30
50
2.20
1.71
®
100
11.15
11.43
100
6.05
6.19
100
4.36
4.31
100
3.51
3.56
100
3.50
2.55
200
20.96
22.05
200
11.29
11.60
200
7.94
7.87
200
6.18
6.13
200
6.12
4.26
300 (max)
30.46
32.67
300 (max)
16.36
17.04
300 (max)
11.51
11.40
300 (max)
8.80
8.75
300 (max)
8.76
6.01
4-20


Features 2'&6;;[[ ® $0,+*  PLFURQ &026 *DWH $UUD Description ODCSXXxx is a family of 4 to 24 mA, non-inverting, CMOS-lev el, output buffer pieces with controlle d slew rate outputs. Logic Symbol Tru th Table ODCSXXxx SL A PADM A PADM LL HH HDL Syntax Verilog ............... ..... ODCSXXxx inst_name (PADM, A); VHD L...................... inst_name: ODCS XXxx port map (PADM, A); Pin Loading Pin Name A (eq-load) ODCSXX04 9.3 Pow er Characteristics Cell Output Drive ( mA) ODCSXX04 4 ODCSXX08 8 ODCSXX12 12 ODCSXX16 16 ODCSXX24 24 a. Se e page 2-15 for power equation. ODCSXX 08 9.3 Load ODCSXX12 9.3 ODCSXX16 9.3 Power Characteristicsa Static IDD (T J = 85°C) (nA) TBD EQLpd (Eq-load) 19 8.6 TBD 220.0 TBD 240.8 TBD 263.6 TBD 282.3 ODCSXX24 11.4 Pad Logic 4-19 2'&6;;[[ $0,+*  PLFURQ &026 *DWH $UUD Propagation Delays (ns) Co nditions: TJ = 25°C, VDD = 5.0V, Typic al Process Capacitive Load (pF) 15 O DCSXX04 From: A tPLH To: PADM tPHL 2.46 2.44 Capacitive .
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