ODCXXE24 Array Datasheet

ODCXXE24 Datasheet, PDF, Equivalent


Part Number

ODCXXE24

Description

CMOS Gate Array

Manufacture

AMI

Total Page 3 Pages
Datasheet
Download ODCXXE24 Datasheet


ODCXXE24
2'&;;([[
®
$0,+*  PLFURQ &026 *DWH $UUD\
Description
ODCXXExx is a family of 1 to 24 mA, non-inverting, CMOS-level, tristate output buffer pieces with active low enables.
Logic Symbol
Truth Table
ODCXXExx
EN
A
PADM
EN A PADM
LL L
LH H
HX Z
HDL Syntax
Verilog .................... ODCXXExx inst_name (PADM, A, EN);
VHDL...................... inst_name: ODCXXExx port map (PADM, A, EN);
Pin Loading
Pin Name
A (eq-load)
EN (eq-load)
PADM (pF)
ODCXXE01
5.6
4.0
4.92
ODCXXE02
7.9
5.3
4.92
ODCXXE04
7.9
5.3
4.93
Load
ODCXXE08
2.3
5.5
4.93
ODCXXE12
2.3
5.5
4.93
Power Characteristics
Cell Output Drive (mA)
ODCXXE01
1
ODCXXE02
2
ODCXXE04
4
ODCXXE08
8
ODCXXE12
12
ODCXXE16
16
ODCXXE24
24
a. See page 2-15 for power equation.
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
TBD
EQLpd (Eq-load)
154.9
TBD
164.2
TBD
174.8
TBD
223.0
TBD
243.9
TBD
268.0
TBD
279.9
ODCXXE16
2.3
5.5
4.93
ODCXXE24
2.3
5.5
4.93
4-23

ODCXXE24
2'&;;([[
$0,+*  PLFURQ &026 *DWH $UUD\
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Capacitive Load (pF)
15
ODCXXE01
From: A
tPLH
To: PADM tPHL
From: EN
tZH
To: PADM tZL
Capacitive Load (pF)
4.70
4.92
4.94
4.98
15
ODCXXE02
From: A
tPLH
To: PADM tPHL
2.53
2.55
From: EN
tZH
To: PADM tZL
Capacitive Load (pF)
2.75
2.62
15
ODCXXE04
From: A
tPLH
To: PADM tPHL
From: EN
tZH
To: PADM tZL
Capacitive Load (pF)
1.65
1.82
1.85
1.72
15
ODCXXE08
From: A
To: PADM
From: EN
To: PADM
tPLH
tPHL
tZH
tZL
1.86
1.57
1.51
1.40
Capacitive Load (pF)
15
ODCXXE12
From: A
tPLH
To: PADM tPHL
From: EN
tZH
To: PADM tZL
Capacitive Load (pF)
1.22
1.61
1.48
1.26
15
ODCXXE16
From: A
tPLH
To: PADM tPHL
2.12
1.59
From: EN
tZH
To: PADM tZL
1.53
1.33
Capacitive Load (pF)
15
ODCXXE24
From: A
To: PADM
From: EN
To: PADM
tPLH
tPHL
tZH
tZL
1.87
1.53
1.42
1.26
25
6.77
7.09
7.05
7.06
50
6.22
6.27
6.39
6.32
50
3.57
3.58
3.67
3.62
50
2.79
2.48
2.48
2.31
50
1.93
2.21
2.20
1.93
50
2.36
2.07
2.13
1.86
50
2.37
1.91
2.04
1.71
4-24
®
35
8.86
9.26
50
12.04
12.53
75 (max)
17.40
18.02
9.16
12.32
17.58
9.18
12.44
18.06
75
8.83
8.94
100
11.42
11.60
150 (max)
16.58
16.89
8.97
11.57
16.83
8.96
11.61
16.96
100 200 300 (max)
6.27
11.58
16.83
6.20
11.51
16.77
6.29
11.61
16.98
6.25
11.49
16.82
100
4.08
3.78
200 300 (max)
6.73 9.43
6.39 8.99
3.83 6.49 9.14
3.58 6.17 8.83
100
2.87
3.03
200 300 (max)
4.69 6.46
4.74 6.53
3.12 4.91 6.72
2.83 4.59 6.31
100
3.04
2.75
200 300 (max)
4.47 5.74
4.07 5.34
2.86 4.23 5.55
2.56 3.89 5.18
100
3.07
2.43
200 300 (max)
4.45 5.80
3.39 4.22
2.78 4.14 5.48
2.26 3.22 4.09


Features 2'&;;([[ ® $0,+*  PLFURQ &026 *DWH $UUD Description ODCXXExx is a family of 1 to 24 mA, non-inverting, CMOS-lev el, tristate output buffer pieces with active low enables. Logic Symbol Trut h Table ODCXXExx EN A PADM EN A PADM LL L LH H HX Z HDL Syntax Verilog .... ................ ODCXXExx inst_name (PA DM, A, EN); VHDL...................... inst_name: ODCXXExx port map (PADM, A, EN); Pin Loading Pin Name A (eq-load) EN (eq-load) PADM (pF) ODCXXE01 5.6 4 .0 4.92 ODCXXE02 7.9 5.3 4.92 ODCXXE0 4 7.9 5.3 4.93 Load ODCXXE08 2.3 5.5 4 .93 ODCXXE12 2.3 5.5 4.93 Power Chara cteristics Cell Output Drive (mA) ODC XXE01 1 ODCXXE02 2 ODCXXE04 4 ODC XXE08 8 ODCXXE12 12 ODCXXE16 16 O DCXXE24 24 a. See page 2-15 for power equation. Power Characteristicsa Sta tic IDD (TJ = 85°C) (nA) TBD EQLpd (E q-load) 154.9 TBD 164.2 TBD 174.8 TBD 223.0 TBD 243.9 TBD 268.0 TBD 279.9 ODCXXE16 2.3 5.5 4.93 ODCXXE2 4 2.3 5.5 4.93 Pad Logic 4-23 Pad Logic 2'&;;([[ $0,+* .
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