ODTSXX24 Datasheet: CMOS Gate Array





ODTSXX24 CMOS Gate Array Datasheet

Part Number ODTSXX24
Description CMOS Gate Array
Manufacture AMI
Total Page 2 Pages
PDF Download Download ODTSXX24 Datasheet PDF

Features: 2'76;;[[ ® $0,+*  PLFURQ &026 *DW H $UUD Description ODTSXXxx is a famil y of 4 to 24 mA, non-inverting, TTL-lev el, output buffer pieces with controlle d slew rate outputs. Logic Symbol Tru th Table ODTSXXxx A SL PADM A PADM LL HH HDL Syntax Verilog ............... ..... ODTSXXxx inst_name (PADM, A); VHD L...................... inst_name: ODTS XXxx port map (PADM, A); Pin Loading Pin Name A (eq-load) ODTSXX04 9.3 Pow er Characteristics Cell Output Drive ( mA) ODTSXX04 4 ODTSXX08 8 ODTSXX12 12 ODTSXX16 16 ODTSXX24 24 a. Se e page 2-15 for power equation. ODTSXX 08 9.3 Load ODTSXX12 9.3 ODTSXX16 9.3 Power Characteristicsa Static IDD (T J = 85°C) (nA) TBD EQLpd (Eq-load) 19 8.6 TBD 220.0 TBD 240.8 TBD 263.6 TBD 282.3 ODTSXX24 11.4 Pad Logic 4-42 ® Propagation Delays (ns) Con ditions: TJ = 25°C, VDD = 5.0V, Typica l Process Capacitive Load (pF) 15 OD TSXX04 From: A tPLH To: PADM tPLH 1 .51 3.60 Capacitive Load (pF) 15 ODTSXX08 From: A tPLH T.

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2'76;;[[
®
$0,+*  PLFURQ &026 *DWH $UUD\
Description
ODTSXXxx is a family of 4 to 24 mA, non-inverting, TTL-level, output buffer pieces with controlled slew rate outputs.
Logic Symbol
Truth Table
ODTSXXxx
A SL
PADM
A PADM
LL
HH
HDL Syntax
Verilog .................... ODTSXXxx inst_name (PADM, A);
VHDL...................... inst_name: ODTSXXxx port map (PADM, A);
Pin Loading
Pin Name
A (eq-load)
ODTSXX04
9.3
Power Characteristics
Cell Output Drive (mA)
ODTSXX04
4
ODTSXX08
8
ODTSXX12
12
ODTSXX16
16
ODTSXX24
24
a. See page 2-15 for power equation.
ODTSXX08
9.3
Load
ODTSXX12
9.3
ODTSXX16
9.3
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
TBD
EQLpd (Eq-load)
198.6
TBD
220.0
TBD
240.8
TBD
263.6
TBD
282.3
ODTSXX24
11.4
4-42

     






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