Document
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Description ODTXXExx is a family of 1 to 24 mA, non-inverting, TTL-level, tristate output buffer pieces with active low enables.
Logic Symbol
Truth Table
ODTXXExx EN A
PADM
EN A PADM
LL
L
LH
H
HX
Z
Z = High Impedance
HDL Syntax Verilog .................... ODTXXExx inst_name (PADM, A, EN); VHDL...................... inst_name: ODTXXExx port map (PADM, A, EN);
Pin Loading
Pin Name
A (eq-load) EN (eq-load) PADM (pF)
ODTXXE01 5.6 4.0 4.92
ODTXXE02 7.9 5.3 4.92
ODTXXE04 7.9 5.3 4.93
Load ODTXXE08
2.3 5.5 4.93
ODTXXE12 2.3 5.5 4.93
ODTXXE16 2.3 5.5 4.93
ODTXXE24 2.3 5.5 4.93
Power Characteristics
Cell
Output Drive (mA)
ODTXXE01 ODTXXE02 ODTXXE04 ODTXXE08 ODTXXE12 ODTXXE16 ODTXXE24
1 2 4 8 12 16 24
a. See page 2-15 for power equation.
Power Characteristicsa
Static IDD (TJ = 85°C) (nA) TBD
EQLpd (Eq-load) 154.9
TBD
164.2
TBD
174.8
TBD
223.0
TBD
243.9
TBD
268.0
TBD
279.9
Pad Logic
4-44
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Propagatio.