LVDS TRANSMITTER. THC63LVDM83D Datasheet

THC63LVDM83D TRANSMITTER. Datasheet pdf. Equivalent

THC63LVDM83D Datasheet
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Part THC63LVDM83D
Description 24bit COLOR LVDS TRANSMITTER
Feature THC63LVDM83D; THC63LVDM83D_Rev.4.30_E THC63LVDM83D 24bit COLOR LVDS TRANSMITTER General Description The THC63LVDM.
Manufacture THine Electronics
Datasheet
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THine Electronics THC63LVDM83D
THC63LVDM83D_Rev.4.30_E
THC63LVDM83D
24bit COLOR LVDS TRANSMITTER
General Description
The THC63LVDM83D transmitter is designed to support pixel
data transmission between Host and Flat Panel Display up to
1080p/WUXGA resolutions.
The THC63LVDM83D converts 28bits of LVCMOS data into
four OpenLDI(LVDS) data streams. The transmitter can be
programmed for rising edge or falling edge clock through a
dedicated pin. At a transmit clock frequency of 160MHz,
24bits of RGB data and 4bits of timing and control data
(HSYNC, VSYNC, DE, CONT1) are transmitted at an
effective rate of 1120Mbps per OpenLDI(LVDS) channel.
Application
Medium and Small Size Panel
Tablet PC / Notebook PC
Security Camera / Industrial Camera
Multi Function Printer
Industrial Equipment
Medical Equipment Monitor
Features
Compatible with TIA/EIA-644 LVDS Standard
7:1 OpenLDI(LVDS) Transmitter
Operating Temperature Range : 0 to +70C
No Special Start-up Sequence Required
Spread Spectrum Clocking Tolerant up to 100kHz Frequency
Modulation and +/-2.5% Deviations.
Wide Dot Clock Range: 8 to 160MHz Suited for
TV Signal : NTSC(12.27MHz) - 1080p(148.5MHz)
PC Signal : QVGA(8MHz) - WUXGA(154MHz)
56pin TSSOP Package
1.2V to 3.3V LVCMOS/ inputs are supported.
LVDS swing is reducible as 200mV by RS-pin to reduce EMI
and power consumption.
PLL requires no external components.
Power Down Mode.
Input clock triggering edge is selectable by R/F-pin
EU RoHS Compliant.
Block Diagram
CMOS/TTL
INPUTS
TA0-6
TB0-6
7
7
TC0-6
7
TD0-6
7
TRANSMITTER
CLKIN
(8 to 160MHz)
R/F
/PDWN
RS
THC63LVDM83D
PLL
DATA
(LVDS)
TA +/-
TB +/-
TC +/-
TD +/-
(56-1120Mbit/On Each
LVDS Channel)
TCLK +/-
CLOCK
(LVDS)
8-160MHz
Figure 1. Block Diagram
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THine Electronics THC63LVDM83D
THC63LVDM83D_Rev.4.30_E
Pin Diagram
Figure 2. Pin Diagram
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THine Electronics THC63LVDM83D
THC63LVDM83D_Rev.4.30_E
Pin Description
Pin Name
Pin #
TA+, TA-
47, 48
TB+, TB-
45, 46
TC+, TC-
41, 42
TD+, TD-
TCLK+,
TCLK-
37, 38
39, 40
TA0 ~ TA6 51, 52, 54, 55, 56, 3, 4
TB0 ~ TB6 6, 7, 11, 12, 14, 15, 19
TC0 ~ TC6 20, 22, 23, 24, 27, 28,
30
TD0 ~ TD6 50, 2, 8, 10, 16, 18, 25
/PDWN
32
Direction
Output
RS 1
Type
LVDS
Description
LVDS Data Out
LVDS Clock Out
Pixel Data Input
H : Normal Operation
L : Power Down (All outputs are Hi-Z)
LVDS Swing Mode, VREF Select See Fig.7,
8
Input
LVCMOS
RS Pin
VCC
0.6 to 1.4V
GND
LVDS
Swing
350mV
350mV
200mV
Small Swing
Input Support
N/A
RS=VREF
N.A
R/F 17
CLKIN
VCC
GND
LVDS VCC
LVDS GND
PLL VCC
PLL GND
31
9, 26
5, 13, 21, 29, 53
44
36, 43 49
34
33, 35
Power
VREF : is Input Reference Voltage
Input Clock Triggering Edge Select
H : Rising Edge
L : Falling Edge
Input Clock
Power Supply Pins for LVCMOS inputs and
digital circuit.
Ground Pins for LVCMOS Inputs and Digital
-
Circuitry.
Power Supply Pins for LVDS Outputs.
Ground Pins for LVDS Outputs.
Power Supply Pin for PLL Circuitry.
Ground Supply Pin for PLL Circuitry.
Table 1. Pin Description
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