Multichip Module. ACT-F128K32 Datasheet

ACT-F128K32 Module. Datasheet pdf. Equivalent

Part ACT-F128K32
Description High Speed 4 Megabit FLASH Multichip Module
Feature ACT–F128K32 High Speed 4 Megabit FLASH Multichip Module Features CIRCUIT TECHNOLOGY www.aeroflex.c.
Manufacture Aeroflex
Datasheet
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ACT-F128K32
ACT–F128K32 High Speed
4 Megabit FLASH Multichip Module
Features
CIRCUIT TECHNOLOGY
www.aeroflex.com
s 4 Low Power 128K x 8 FLASH Die in One MCM
Package
s Organized as 128K x 32
q User Configurable to 256K x 16 or 512K x 8
q Upgradable to 512K x 32 in same Package Style
s Access Times of 60, 70, 90, 120 and 150ns
s +5V Programing, 5V ±10% Supply
s 100,000 Erase/Program Cycles Typical, 0°C to +70°C
s Low Standby Current
s TTL Compatible Inputs and CMOS Outputs
s Embedded Erase and Program Algorithms
s Page Program Operation and Internal Program
Control Time
s Commercial, Industrial and Military Temperature
Ranges
s MIL-PRF-38534 Compliant MCMs Available
s Industry Standard Pinouts
s Packaging – Hermetic Ceramic
q 68 Lead, .88" x .88" x .160" Single-Cavity Small
Outline gull wing, Aeroflex code# "F5" (Drops into
the 68 Lead JEDEC .99"SQ CQFJ footprint)
q 66 Pin, 1.08" x 1.08" x .160" PGA Type, No
Shoulder, Aeroflex code# "P3"
q 66 Pin, 1.08" x 1.08" x .185" PGA Type, With
Shoulder, Aeroflex code# "P7"
s Sector Architecture (Each Die)
q 8 Equal size sectors of 64K bytes each
q Any Combination of Sectors can be erased with
one command sequence
q Supports Full Chip Erase
s DESC SMD# 5962–94716 Released (P3,P7,F5)
Block Diagram – PGA Type Package(P3,P7) & CQFP(F5)
WE1 CE1 WE2 CE2 WE3 CE3 WE4 CE4
OE
A0–A16
128Kx8 128Kx8 128Kx8 128Kx8
8
I/O0-7
88
8
I/O8-15 I/O16-23 I/O24-31
Pin Description
I/O0-31 Data I/O
A0–16 Address Inputs
WE1-4 Write Enables
CE1-4 Chip Enables
OE Output Enable
VCC Power Supply
GND
Ground
NC Not Connected
General Description
The ACT–F128K32 is a high
speed, 4 megabit CMOS flash
multichip module (MCM)
designed for full temperature
range military, space, or high
reliability applications.
The MCM can be organized
as a 128K x 32 bits, 256K x 16
bits or 512K x 8 bits device and
is input TTL and output CMOS
compatible. The command
register is written by bringing
WE to a logic low level (VIL),
while CE is low and OE is at
logic high level (VIH). Reading is
accomplished by chip Enable
(CE) and Output Enable (OE)
being logically active, see
Figure 9. Access time grades of
60ns, 70ns, 90ns, 120ns and
150ns maximum are standard.
The ACT–F128K32 is
packaged in a hermetically
eroflex Circuit Technology - Advanced Multichip Modules © SCD1667 REV A 4/28/98



ACT-F128K32
General Description, Cont’d,
sealed co-fired ceramic 66 pin, 1.08" sq
PGA or a 68 lead, .88" sq Ceramic Gull
Wing CQFP package for operation over the
temperature range of -55°C to +125°C and
military environment.
Each flash memory die is organized as
128KX8 bits and is designed to be
programmed in-system with the standard
system 5.0V Vcc supply. A 12.0V VPP is
not required for write or erase operations.
The MCM can also be reprogrammed with
standard EPROM programmers (with the
proper socket).
The standard ACT-F128K32 offers
access times between 60ns and 150ns,
allowing operation of high-speed
microprocessors without wait states. To
eliminate bus contention, the device has
separate chip enable (CE) and write enable
(WE). The ACT-F128K32 is command set
compatible with JEDEC standard 1 Mbit
EEPROMs. Commands are written to the
command register using standard
microprocessor write timings. Register
contents serve as input to an internal
state-machine which controls the erase and
programming circuitry. Write cycles also
internally latch addresses and data needed
for the programming and erase operations.
Reading data out of the device is similar
to reading from 12.0V Flash or EPROM
devices. The ACT-F128K32 is programmed
by executing the program command
sequence. This will invoke the Embedded
Program Algorithm which is an internal
algorithm that automatically times the
program pulse widths and verifies proper
cell margin. Typically, each sector can be
programmed and verified in less than 0.3
second. Erase is accomplished by
executing the erase command sequence.
This will invoke the Embedded Erase
Algorithm which is an internal algorithm
that automatically preprograms the array, (if
it is not already programmed before)
executing the erase operation. During
erase, the device automatically times the
erase pulse widths and verifies proper cell
margin.
Each die in the module or any individual
sector of the die is typically erased and
verified in 1.3 seconds (if already
completely preprogrammed).
Each die also features a sector erase
architecture. The sector mode allows for
16K byte blocks of memory to be erased
and reprogrammed without affecting other
blocks. The ACT-F128K32 is erased when
shipped from the factory.
The device features single 5.0V power
supply operation for both read and write
functions. lnternally generated and
regulated voltages are provided for the
program and erase operations. A low VCC
detector automatically inhibits write
operations on the loss of power. The end of
program or erase is detected by Data
Polling of D7 or by the Toggle Bit feature on
D6. Once the end of a program or erase
cycle has been completed,-+ the device
internally resets to the read mode.
All bits of each die, or all bits within a
sector of a die, are erased via
Fowler-Nordhiem tunneling. Bytes are
programmed one byte at a time by hot
electron injection.
DESC Standard Military Drawing (SMD)
numbers are released.
Aeroflex Circuit Technology
2 SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700





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