Multichip Module. ACT-F512K32 Datasheet

ACT-F512K32 Module. Datasheet pdf. Equivalent

Part ACT-F512K32
Description High Speed 16 Megabit FLASH Multichip Module
Feature ACT–F512K32 High Speed 16 Megabit FLASH Multichip Module Features CIRCUIT TECHNOLOGY www.aeroflex..
Manufacture Aeroflex
Download ACT-F512K32 Datasheet

ACT–F512K32 High Speed 16 Megabit FLASH Multichip Module Fe ACT-F512K32 Datasheet
Recommendation Recommendation Datasheet ACT-F512K32 Datasheet

ACT–F512K32 High Speed
16 Megabit FLASH Multichip Module
4 Low Power 512K x 8 FLASH Die in One MCM
TTL Compatible Inputs and CMOS Outputs
Access Times of 60, 70, 90, 120 and 150ns
+5V Programing, 5V ±10% Supply
100,000 Erase/Program Cycles
Low Standby Current
Page Program Operation and Internal Program
Control Time
Sector Architecture (Each Die)
8 Equal size sectors of 64K bytes each
Any Combination of Sectors can be erased with
one command sequence
Supports full chip erase
Embedded Erase and Program Algorithms
MIL-PRF-38534 Compliant MCMs Available
Industry Standard Pinouts
Packaging – Hermetic Ceramic
68 Lead, .88" x .88" x .160" Single-Cavity Small
Outline gull wing, Aeroflex code# "F5" (Drops into
the 68 Lead JEDEC .99"SQ CQFJ footprint)
66 Pin, 1.08" x 1.08" x .160" PGA Type, No
Shoulder, Aeroflex code# "P3"
66 Pin, 1.08" x 1.08" x .185" PGA Type, With
Shoulder, Aeroflex code# "P7"
Internal Decoupling Capacitors for Low Noise
Commercial, Industrial and Military Temperature
DESC SMD# 5962–94612
Released (P3,P7,F5)
Block Diagram – PGA Type Package(P3,P7) & CQFP(F5)
A0 A18
512Kx8 512Kx8 512Kx8 512Kx8
88 8
I/O8-15 I/O16-23 I/O24-31
Pin Description
I/O0-31 Data I/O
A0–18 Address Inputs
WE1-4 Write Enables
CE1-4 Chip Enables
OE Output Enable
VCC Power Supply
NC Not Connected
General Description
The ACT–F512K32 is a high
speed, 16 megabit CMOS flash
multichip module (MCM)
designed for full temperature
range military, space, or high
reliability applications.
The MCM can be organized
as a 512K x 32bits, 1M x 16bits
or 2M x 8bits device and is input
TTL and output CMOS
compatible. The command
register is written by bringing
WE to a logic low level (VIL),
while CE is low and OE is at
logic high level (VIH). Reading is
accomplished by chip Enable
(CE) and Output Enable (OE)
being logically active, see
Figure 9. Access time grades of
60ns, 70ns, 90ns, 120ns and
150ns maximum are standard.
The ACT–F512K32 is
packaged in a hermetically
eroflex Circuit Technology - Advanced Multichip Modules © SCD1665 REV B 6/29/01

General Description, Cont’d,
sealed co-fired ceramic 66 pin, 1.08"SQ PGA
or a 68 lead, .88"SQ Ceramic Gull Wing CQFP
package for operation over the temperature
range of -55°C to +125°C and military
Each flash memory die is organized as
512KX8 bits and is designed to be
programmed in-system with the standard
system 5.0V Vcc supply. A 12.0V VPP is not
required for write or erase operations. The
MCM can also be reprogrammed with standard
EPROM programmers (with the proper socket).
The standard ACT–F512K32 offers access
times between 60ns and 150ns, allowing
operation of high-speed microprocessors
without wait states. To eliminate bus
contention, the device has separate chip
enable (CE) and write enable (WE). The
ACT-F512K32 is command set compatible with
JEDEC standard 4 Mbit EEPROMs.
Commands are written to the command
register using standard microprocessor write
timings. Register contents serve as input to an
internal state-machine which controls the
erase and programming circuitry. Write cycles
also internally latch addresses and data
needed for the programming and erase
Reading data out of the device is similar to
reading from 12.0V Flash or EPROM devices.
The ACT-F512K32 is programmed by
executing the program command sequence.
This will invoke the Embedded Program
Algorithm which is an internal algorithm that
automatically times the program pulse widths
and verifies proper cell margin. Typically, each
sector can be programmed and verified in less
than one second. Erase is accomplished by
executing the erase command sequence. This
will invoke the Embedded Erase Algorithm
which is an internal algorithm that
automatically preprograms the array, (if it is not
already programmed) before executing the
erase operation. During erase, the device
automatically times the erase pulse widths and
verifies proper cell margin.
Each die in the module or any individual
sector of the die is typically erased and verified
in 1.5 seconds (if already completely
Each die also features a sector erase
architecture. The sector mode allows for 64K
byte blocks of memory to be erased and
reprogrammed without affecting other blocks.
The ACT-F512K32 is erased when shipped
from the factory.
The device features single 5.0V power
supply operation for both read and write
functions. lnternally generated and regulated
voltages are provided for the program and
erase operations. A low VCC detector
automatically inhibits write operations on the
loss of power. The end of program or erase is
detected by Data Polling of D7 or by the Toggle
Bit feature on D6. Once the end of a program
or erase cycle has been completed, the device
internally resets to the read mode.
All bits of each die, or all bits within a
sector of a die, are erased via
Fowler-Nordhiem tunneling. Bytes are
programmed one byte at a time by hot electron
DESC Standard Military Drawing (SMD)
numbers are released.
Aeroflex Circuit Technology
2 SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700

@ 2014 :: :: Semiconductors datasheet search & download site (Privacy Policy & Contact)