D-type flip-flop. 74LVC1G74-Q100 Datasheet

74LVC1G74-Q100 flip-flop. Datasheet pdf. Equivalent


Part 74LVC1G74-Q100
Description Single D-type flip-flop
Feature 74LVC1G74-Q100 Single D-type flip-flop with set and reset; positive edge trigger Rev. 4 — 25 January.
Manufacture nexperia
Datasheet
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74LVC1G74-Q100 Single D-type flip-flop with set and reset; p 74LVC1G74-Q100 Datasheet
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74LVC1G74-Q100
74LVC1G74-Q100
Single D-type flip-flop with set and reset;
positive edge trigger
Rev. 4 — 25 January 2019
Product data sheet
1. General description
The 74LVC1G74-Q100 is a single positive edge triggered D-type flip-flop. It has individual data (D)
inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q outputs.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing damaging backflow current through the device when it is powered
down.
The set and reset are asynchronous active LOW inputs and operate independently of the clock
input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition
of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock
transition for predictable operation. Schmitt trigger action at all inputs makes the circuit highly
tolerant of slower input rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V



74LVC1G74-Q100
Nexperia
74LVC1G74-Q100
Single D-type flip-flop with set and reset; positive edge trigger
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74LVC1G74DP-Q100 -40 °C to +125 °C
74LVC1G74DC-Q100 -40 °C to +125 °C
74LVC1G74GT-Q100 -40 °C to +125 °C
Name
TSSOP8
VSSOP8
XSON8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
plastic extremely thin small outline package;
no leads; 8 terminals; body 1 × 1.95 × 0.5 mm
Version
SOT505-2
SOT765-1
SOT833-1
4. Marking
Table 2. Marking codes
Type number
74LVC1G74DP-Q100
74LVC1G74DC-Q100
74LVC1G74GT-Q100
Marking code [1]
V74
V74
V74
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
SD
SD
DD
QQ
CP CP
FF Q
Q
RD
RD 001aah757
Fig. 1. Logic symbol
C
S
C1
1D
R
001aah758
Fig. 2. IEC logic symbol
C
Q
D
RD
SD
CP
Fig. 3. Logic diagram
C
C
C
C
C
C
C
C
mna421
Q
74LVC1G74_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 January 2019
© Nexperia B.V. 2019. All rights reserved
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