Clock Generator. 5P49V6968 Datasheet

5P49V6968 Generator. Datasheet pdf. Equivalent


Part 5P49V6968
Description Clock Generator
Feature VersaClock® 6E Programmable Clock Generator 5P49V6968 Datasheet Description The 5P49V6968 is a pro.
Manufacture IDT
Datasheet
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VersaClock® 6E Programmable Clock Generator 5P49V6968 Datas 5P49V6968 Datasheet
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5P49V6968
VersaClock® 6E Programmable
Clock Generator
5P49V6968
Datasheet
Description
The 5P49V6968 is a programmable clock generator that is
intended for high-performance consumer, networking, industrial,
computing, and data communications applications. This is IDT’s
sixth generation of programmable clock technology
(VersaClock 6E).
The 5P49V6968 generates the frequencies from a single
reference clock, which can originate from one of the two
redundant clock inputs. A glitchless manual switchover function
allows one of the redundant clocks to be selected during normal
operation.
Two select pins allow up to four different configurations to be
programmed, and can be used for different operating modes.
Typical Applications
Ethernet switch/router
PCI Express 1.0/2.0/3.0/4.0
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fiber Channel, SAN
Telecom line cards
Datacenter
Block Diagram
XIN/REF
XOUT
CLKSEL
SD/OE
SEL1/SDA
SEL0/SCL
VDDA
VDDD
OTP
and
Control
Logic
PLL
Features
Flexible 1.8V, 2.5V, and 3.3V power rails
High-performance, low phase noise PLL, < 0.5ps RMS typical
phase jitter on outputs
Four banks of internal OTP memory
— In-system or factory programmable
I2C serial programming interface
— 0xD0 or 0xD4 I2C address options allow multiple devices
to be configured in a same system
Reference LVCMOS output clock
Three universal configurable outputs (OUT1, 2, 4):
— Differential (LVPECL, LVDS, or HCSL)
1kHz to 350MHz
— Two single-ended (in-phase or 180 degrees out of phase)
1kHz to 200MHz
— I/O VDDs can be mixed and matched, supporting 1.8V
(LVDS and LVCMOS), 2.5V, or 3.3V
— Independent spread spectrum on each output pair
Eight additional LPHCSL outputs (OUT 3, 5–11)
— 1.8V low power supply
— 1kHz to 200MHz
Programmable output enable or power-down mode
Redundant clock inputs with manual switchover
Available in 6 × 6 mm 48-VFQFPN package
-40° to +85°C industrial temperature operation
FOD1
FOD2
FOD3
FOD4
VDDO0
OUT0_SEL_I2CB
VDDO1
OUT1
OUT1B
VDDO2
OUT2
OUT2B
OEA
OUT3, 5, 6, 11
OEB
OUT7, 8, 9, 10
VDDO4
OUT4
OUT4B
© 2018 Integrated Device Technology, Inc.
1
August 30, 2018



5P49V6968
5P49V6968 Datasheet
Contents
1. Pin Assignments...........................................................................................................................................................................................3
2. Pin Descriptions............................................................................................................................................................................................3
3. Absolute Maximum Ratings..........................................................................................................................................................................6
4. Thermal Characteristics................................................................................................................................................................................6
5. Recommended Operating Conditions ..........................................................................................................................................................6
6. Electrical Characteristics ..............................................................................................................................................................................7
7. Test Loads..................................................................................................................................................................................................14
8. Jitter Performance Characteristics .............................................................................................................................................................15
9. PCI Express Jitter Performance and Specification.....................................................................................................................................16
10. Features and Functional Blocks .................................................................................................................................................................17
10.1 Device Startup and Power-on-Reset................................................................................................................................................17
10.2 Internal Crystal Oscillator (XIN/REF) ...............................................................................................................................................18
10.2.1 Choosing Crystals.............................................................................................................................................................18
10.2.2 Tuning the Crystal Load Capacitor....................................................................................................................................18
10.3 Programmable Loop Filter................................................................................................................................................................20
10.4 Fractional Output Dividers (FOD).....................................................................................................................................................20
10.4.1 Individual Spread Spectrum Modulation ...........................................................................................................................20
10.4.2 Bypass Mode ....................................................................................................................................................................20
10.4.3 Cascaded Mode................................................................................................................................................................20
10.4.4 Dividers Alignment ............................................................................................................................................................20
10.4.5 Programmable Skew.........................................................................................................................................................21
10.5 Output Drivers..................................................................................................................................................................................21
10.6 SD/OE Pin Function.........................................................................................................................................................................21
10.7 I2C Operation ...................................................................................................................................................................................22
11. Typical Application Circuit ..........................................................................................................................................................................23
11.1 Input – Driving the XIN/REF.............................................................................................................................................................24
11.1.1 Driving XIN/REF with a CMOS Driver ...............................................................................................................................24
11.1.2 Driving XIN with a LVPECL Driver ....................................................................................................................................25
11.2 Output – Single-ended or Differential Clock Terminations ...............................................................................................................26
11.2.1 LVDS Termination.............................................................................................................................................................26
11.2.2 LVPECL Termination ........................................................................................................................................................27
11.2.3 HCSL Termination.............................................................................................................................................................28
11.2.4 LVCMOS Termination.......................................................................................................................................................28
12. Package Outline Drawings .........................................................................................................................................................................29
13. MarkingDiagram.........................................................................................................................................................................................29
14. OrderingInformation ...................................................................................................................................................................................29
15. RevisionHistory ..........................................................................................................................................................................................30
© 2018 Integrated Device Technology, Inc.
2
August 30, 2018







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