Programmable Clock. 5P49V6975 Datasheet

5P49V6975 Clock. Datasheet pdf. Equivalent


Part 5P49V6975
Description 6E Programmable Clock
Feature VersaClock® 6E Programmable Clock with Internal Crystal 5P49V6975 Datasheet Description The 5P49V6.
Manufacture IDT
Datasheet
Download 5P49V6975 Datasheet


VersaClock® 6E Programmable Clock with Internal Crystal 5P4 5P49V6975 Datasheet
VersaClock® 6E Programmable Clock with Internal Crystal 5P4 5P49V6975 Datasheet
Recommendation Recommendation Datasheet 5P49V6975 Datasheet




5P49V6975
VersaClock® 6E Programmable
Clock with Internal Crystal
5P49V6975
Datasheet
Description
The 5P49V6975 is a programmable clock generator intended for
high-performance consumer, networking, industrial, computing,
and data-communications applications. The device is a member of
IDT’s sixth generation of programmable clock technology,
VersaClock 6E.
The 5P49V6975 contains an internal crystal, which eliminates the
need for external crystal and load cap tuning.
Two select pins allow up to four different configurations to be
programmed, and can be used for different operating modes (full
function, partial function, partial power-down), regional standards
(US, Japan, Europe) or system production margin testing. The
5P49V6975 can be configured to use one of two I2C addresses to
allow the use of multiple devices in a system.
Typical Applications
Ethernet switch/router
PCI Express 1–4
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fiber Channel, SAN
Telecom line cards
Laser distance sensing
Block Diagram
CLKIN
CLKINB
CLKSEL
SD/OE
SEL1/SDA
SEL0/SCL
VDDA
VDDD
OTP
and
Control
Logic
PLL
Features
Internal crystal input integrated into package
Flexible 1.8V, 2.5V, 3.3V power rails
High-performance, low phase noise PLL, < 0.5ps RMS typical
phase jitter on outputs
Four banks of internal OTP memory
— In-system or factory programmable
— Two select pins accessible with processor GPIOs or
bootstrapping
I2C serial programming interface
— 0xD0 or 0xD4 I2C address options allow multiple devices
configured in a same system
Reference LVCMOS output clock
Four universal output pairs individually configurable:
— Differential (LVPECL, LVDS, or HCSL)
— Two single-ended (2 LVCMOS in-phase or 180 degrees
out of phase)
— I/O VDDs can be mixed and matched, supporting 1.8V
(LVDS and LVCMOS), 2.5V, or 3.3V
— Independent spread spectrum on each output pair
Output frequency ranges:
— LVCMOS clock outputs: 1kHz to 200MHz
— LVDS, LVPECL, HCSL differential clock outputs: 1kHz to
350MHz
Programmable output enable or power-down mode
Available in 4 × 4 mm 24-LGA package
-40° to +85°C industrial temperature operation
FOD1
FOD2
FOD3
FOD4
VDDO0
OUT0_SEL_I2CB
VDDO1
OUT1
OUT1B
VDDO2
OUT2
OUT2B
VDDO3
OUT3
OUT3B
VDDO4
OUT4
OUT4B
© 2018 Integrated Device Technology, Inc.
1
April 27, 2018



5P49V6975
5P49V6975 Datasheet
Contents
1. Pin Assignments...........................................................................................................................................................................................3
2. Pin Descriptions............................................................................................................................................................................................3
3. Absolute Maximum Ratings..........................................................................................................................................................................5
4. Thermal Characteristics................................................................................................................................................................................5
5. Recommended Operating Conditions ..........................................................................................................................................................5
6. Electrical Characteristics ..............................................................................................................................................................................6
7. Test Loads..................................................................................................................................................................................................13
8. Jitter Performance Characteristics .............................................................................................................................................................14
9. PCI Express Jitter Performance and Specification.....................................................................................................................................15
10. Features and Functional Blocks .................................................................................................................................................................16
10.1 Device Startup and Power-on-Reset................................................................................................................................................16
10.2 Reference Clock and Selection........................................................................................................................................................17
10.3 Manual Switchover...........................................................................................................................................................................17
10.4 Programmable Loop Filter................................................................................................................................................................18
10.5 Fractional Output Dividers (FOD).....................................................................................................................................................18
10.5.1 Individual Spread Spectrum Modulation ...........................................................................................................................18
10.5.2 Bypass Mode ....................................................................................................................................................................18
10.5.3 Cascaded Mode................................................................................................................................................................18
10.5.4 Dividers Alignment ............................................................................................................................................................18
10.5.5 Programmable Skew.........................................................................................................................................................19
10.6 Output Drivers..................................................................................................................................................................................19
10.7 SD/OE Pin Function.........................................................................................................................................................................19
10.8 I2C Operation ...................................................................................................................................................................................20
11. Typical Application Circuit ..........................................................................................................................................................................21
11.1 Input – Driving the CLKIN ................................................................................................................................................................22
11.1.1 Wiring the CLKIN Pin to Accept Single-Ended Inputs.......................................................................................................22
11.1.2 Driving CLKIN with Differential Clock................................................................................................................................23
11.2 Output – Single-ended or Differential Clock Terminations ...............................................................................................................23
11.2.1 LVDS Termination.............................................................................................................................................................23
11.2.2 LVPECL Termination ........................................................................................................................................................24
11.2.3 HCSL Termination.............................................................................................................................................................25
11.2.4 LVCMOS Termination.......................................................................................................................................................25
12. Package Outline Drawings .........................................................................................................................................................................25
13. MarkingDiagram.........................................................................................................................................................................................26
14. OrderingInformation ...................................................................................................................................................................................26
15. RevisionHistory ..........................................................................................................................................................................................26
© 2018 Integrated Device Technology, Inc.
2
April 27, 2018







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