Density PLD. ISPLSI1032 Datasheet

ISPLSI1032 PLD. Datasheet pdf. Equivalent


Lattice Semiconductor ISPLSI1032
ispLSI® 1032
In-System Programmable High Density PLD
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High Speed Global Interconnect
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 90 MHz Maximum Operating Frequency
fmax = 60 MHz for Industrial and Military/883 Devices
tpd = 12 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
Functional Block Diagram
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
A0 C7
A1 D Q C6
A2
Logic D Q
C5
A3
Array D Q GLB
C4
A4 C3
DQ
A5 C2
A6 C1
A7 Global Routing Pool (GRP) C0
B0 B1 B2 B3 B4 B5 B6 B7
CLK
Output Routing Pool
Description
The ispLSI 1032 is a High-Density Programmable Logic
Device containing 192 Registers, 64 Universal I/O pins,
eight Dedicated Input pins, four Dedicated Clock Input
pins and a Global Routing Pool (GRP). The GRP pro-
vides complete interconnectivity between all of these
elements. The ispLSI 1032 features 5-Volt in-system
programming and in-system diagnostic capabilities. It is
the first device which offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1032 device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see figure 1). There are a total of 32 GLBs in the
ispLSI 1032 device. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
January 2002
1032_08
1


ISPLSI1032 Datasheet
Recommendation ISPLSI1032 Datasheet
Part ISPLSI1032
Description In-System Programmable High Density PLD
Feature ISPLSI1032; ispLSI® 1032 In-System Programmable High Density PLD OutputDISCALOLNTDIENVUIECDERoutingSPool Output.
Manufacture Lattice Semiconductor
Datasheet
Download ISPLSI1032 Datasheet




Lattice Semiconductor ISPLSI1032
Specifications ispLSI 1032
Functional Block Diagram
Figure 1. ispLSI 1032 Functional Block Diagram
RESET
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O I/O I/O I/O I/O I/O I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O IN IN
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 7 6
Generic
Logic Blocks
(GLBs)
Input Bus
Output Routing Pool (ORP)
D7 D6 D5 D4 D3 D2 D1 D0
C7
A0
C6
A1
C5
A2
C4
Global
A3 Routing
Pool
C3
(GRP)
A4
C2
A5
C1
A6
C0
A7
IN 5
IN 4
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
SDI/IN 0
MODE/IN 1
Megablock
ispEN
SDO/IN 2
SCLK/IN 3
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool (ORP)
Input Bus
Clock
Distribution
Network
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
YYYY
0123
0139(1)-32-isp
The device also has 64 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put, latched input, output or bi-directional I/O pin with
3-state control. Additionally, all outputs are polarity se-
lectable, active high or active low. The signal levels are
TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. The I/O cells
within the Megablock also share a common Output
Enable (OE) signal. The ispLSI 1032 device contains four
of these Megablocks.
The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1032 device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (C0 on the ispLSI
1032 device). The logic of this GLB allows the user to
create an internal clock from a combination of internal
signals within the device.
2



Lattice Semiconductor ISPLSI1032
Specifications ispLSI 1032
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
VCC
VIL
VIH
PARAMETER
Supply Voltage
Input Low Voltage
Input High Voltage
Commercial
Industrial
Military/883
TA = 0°C to +70°C
TA = -40°C to +85°C
TC = -55°C to +125°C
MIN.
4.75
4.5
4.5
0
2.0
Capacitance (TA=25oC, f=1.0 MHz)
MAX.
UNITS
5.25
5.5 V
5.5
0.8 V
Vcc + 1
V
Table 2- 0005Aisp w/mil.eps
SYMBOL
C1
PARAMETER
Dedicated Input Capacitance
C2 I/O and Clock Capacitance
1. Guaranteed but not 100% tested.
Commercial/Industrial
Military
Data Retention Specifications
MAXIMU1M
8
10
10
UNITS
pf
pf
pf
TEST CONDITIONS
VCC=5.0V, VIN=2.0V
VCC=5.0V, VIN=2.0V
VCC=5.0V, VI/O, VY=2.0V
Table 2- 0006
PARAMETER
Data Retention
Erase/Reprogram Cycles
MINIMUM
20
10000
MAXIMUM
UNITS
Years
Cycles
Table 2- 0008B
3







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