High Density Programmable Logic
ispLSI® 3256
High Density Programmable Logic
ispLSI 3256A
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC — 128 I/O Pins — ...
Description
ispLSI® 3256
High Density Programmable Logic
ispLSI 3256A
Features
HIGH-DENSITY PROGRAMMABLE LOGIC — 128 I/O Pins — 11000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic
HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 77 MHz Maximum Operating Frequency — tpd = 15 ns Propagation Delay
— TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power
IN-SYSTEM PROGRAMMABLE — In-System Programmable™ (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging
100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE...
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