Tone Decoder. XR-2567 Datasheet

XR-2567 Decoder. Datasheet pdf. Equivalent


Exar XR-2567
XR·2567
Dual Monolithic Tone Decoder
GENERAL DESCRIPTION
The XR-2567 is a dual monolithic tone decoder of the
567-type that is ideally suited for tone or frequency de-
coding in multiple-tone communication systems. Each
decoder of the XR-2567 can be used independently or
both sections can be interconnected for dual opera-
tion. The matching and temperature tracking charac-
teristics between decoders on this monolithic chip are
superior to those available from two separate tone de-
coder packages.
The XR-2567 operates over a frequency range of 0.01
Hz to 500 kHz. Supply voltages can vary from 4.5V to
12V, with internal voltage regulation provided for sup-
plies between 7V and 12V. Each decoder consists of a
phase-locked loop (PLL), a quadrature AM detector, a
voltage comparator, and a logic compatible output that
can sink more than 100 mA of load current.
The center frequency of each decoder is set by an ex-
ternal resistor and capacitor which determine the free-
running frequency of each PLL. When an input tone is
present within the passband of the circuit, the PLL
"locks" on the input signal. The logic output, which is
normally "high", then switches to a "low" state during
this "lock" condition.
FEATURES
Replaces two 567-type decoders
Excellent temperature tracking between decoders
Bandwidth adjustable from 0 to 14 %
Logic compatible outputs with 100 mA sink capability
Center frequency matching (1 % typ.)
Center frequency adjustable from 0.01 Hz to 500 kHz
Inherent immunity to false triggering
Frequency range adjustable over 20:1 range by
external resistor.
APPLICATIONS
Touch-Tone~ Decoding
Sequential Tone Decoding
Dual-Tone Decoding/
Encoding
Communications Paging
Ultrasonic Remote-
Control and Monitoring
Full-Duplex Carrier-Tone
Transceiver
Wireless Intercom
Dual Precision
Oscillator
FSK Generation and
Detection
ABSOLUTE MAXIMUM RATINGS
Power Supply
With Internal Regulator
14V
Without Regulator (Pins 12 and 13 shorted) 10V
Power Dissipation
Ceramic Package
750 mW
Derate Above + 25°C
6 mW/oC
Plastic Package
625 mW/oC
Derate Above + 25°C
5.5 mW/oC
FUNCTIONAL BLOCK DIAGRAM
Operating Temperature
XR-2567M
XR-2567C
Storage Temperature
ORDERING INFORMATION
Part Number
Package
XR-2567CN
XR-2567CP
Ceramic
Plastic
- 55°C to + 125DC
ODC to + 70 DC
- 65 DC to + 150DC
Temperature Range
ODC to + 70DC
ODC to + 70DC
SYSTEM DESCRIPTION
The XR-2567 dual monolithic tone decoder consists of
two independant 567-type circuits and an on board volt-
age regulator. Each decoder has a phase detector, low
pass filter, and current controlled oscillator which com-
prise the basic phase locked loop, plus an additional
low pass filter and quadrature detector enabling detec-
tion of in-band signals. Both devices have normally high
open collector outputs capable of sinking 100 mA.
The input signal is applied to Pin 14 (device A) or Pin 11
(device B), both with 20 kG nominal input resistance.
Free running frequency is controlled by an RC network
at Pins 1 and 16 (device A) or Pins 8 and 9 (device B). A
capacitor on Pin 2 (A), or Pin 7 (B) serves as the output
filter and eliminates out-of-band triggering. PLL filtering
is accomplished with a capacitor on Pin 15 (A), or Pin
10 (B); bandwidth and skew are also dependant upon
the circuitry here. Bandwidth is adjustable from 0% to
14% of the center frequency. Pin 13 is +VCC (4.75 to
12V nominal, 14V maximum); Pin 7 is ground; and Pin 3
(A) or Pin 6 (B) is the open collector output, pulling low
when an in-band signal triggers the device.
Voltage supplies below 7V necessitate bypassing the
internal regulator. This is accomplished by shorting Pin
12 to VCC; for supplies over 7V, a bypass capacitor of
at least 1 IJ.F should AC ground Pin 12.
I
6-115


XR-2567 Datasheet
Recommendation XR-2567 Datasheet
Part XR-2567
Description Dual Monolithic Tone Decoder
Feature XR-2567; XR·2567 Dual Monolithic Tone Decoder GENERAL DESCRIPTION The XR-2567 is a dual monolithic tone de.
Manufacture Exar
Datasheet
Download XR-2567 Datasheet




Exar XR-2567
XR·2567
ELECTRICAL CHARACTERISTICS
Test Conditions: Vee = + 5V, TA = 25° e, unless otherwise specified.Test circuit of Figure 2, 81 closed unless
otherwise specified.
PARAMETERS
MIN
GENERAL
Supply Voltage Range
Without Regulator
With Internal Regulator
Supply Current (both decoders)
Quiescent XR·2567M
XR-2567C
Activated XR-2567M
XR-2567C
Output Voltage
Negative Voltage at Input
Positive Voltage at Input
CENTER FREQUENCY (each decoder section)
Highest Center Frequency
Center Frequency Stability
Temperature TA = 25°C
OO<TA<+70°C
-55°<TA<+125°C
Supply Voltage
Without Regulator
XR-2567M
XR-2567C
With Internal Regulator
XR-2567M
XR-2567C
4.75
6.5
100
DETECTION BANDWIDTH
(each decoder section)
Largest Detection Bandwidth
XR-2567M
XR-2567C
Largest Detection Bandwidth Skew
XR-2567M
XR-2567C
Largest Detection Bandwidth Variation
Temperature
Supply Voltage
INPUT (each decoder section)
Input Resistance
Smallest Detectable Input Voltage
Largest No-Output Input Voltage
Greatest Simultaneous Outband
Signal to Inband Signal Ratio
Minimum Input Signal to Wideband
Noise Ratio
OUTPUT (each decoder section)
Output Saturation Voltage
12
10
10
Output Leakage Current
Fastest ON-OFF Cycling Rate
Output Rise Time
Output Fall Time
MATCHING CHARACTERISTICS
Center Frequency Matching
Temperature Dritt Matching
LIMITS
TYP MAX
12
14
22
24
500
35
±60
±140
7
12
16
20
26
30
15
-10
VCC+0.5
0.5
0.7
0.05
0.1
1.0
2.0
14
14
1
1
±0.1
±2
20
20
15
+6
-6
0.2
0.6
0.01
tn/20
150
30
1
±20
±50
16
18
2
3
25
0.4
1.0
25
UNITS
Vdc
Vdc
mA
mA
mA
mA
V
V
V
kHz
ppmloC
ppmloC
ppmloC
%N
%N
%N
%N
% otto
% otto
% otto
% otto
%IOC
%N
kO
mVrms
mVrms
dB
dB
V
V
p.A
ns
ns
%
ppmloC
ppmloC
CONDITIONS
See Figure 5, S1 closed.
See Figure 5, S1 open.
See Figure 7, 8
RL = 20 kO
RL = 20 kO
RL = 20 kO
RL = 20 kO
See Figure 14
See Figure 14
See Figure 14
to = 100 kHz
to = 100 kHz
to = 100 kHz, VCC = 9V
to = 100 kHz, VCC = 9V
to = 100 kHz
to = 100 kHz
Yin = 300 mV rms
Vin = 300 mV rms
IL = 100 mA, ti = to
IL = 100 mA, ti = to
Noise BW = 140 kHz
IIL = 30 mA, Yin = 25 mV rms I
IL = 100 mA, Vin = 25 mV rms
RL = 500
RL = 500
to = 10 kHz
O°C<TA <70°C
- 55°C<TA < 125°C
6-116



Exar XR-2567
OUTPUT
Figure 2. Test Circuit
OUTPUT
!B
Response to 100 mV rms tone burst
RL c 100 ohms
Figure 3. XR-2567 Typical Response
DEFINITIONS OF XR-2567 PARAMETERS
fo is the free-running frequency of the current-
controlled oscillator of the PLL with no input signal. It is
determined by resistor Rl and capacitor Cl; fo can be
approximated by
The largest detection bandwidth is the largest frequen-
cy range within which an input signal above the thresh-
old voltage will cause a logical zero state at the output.
The maximum detection bandwidth corresponds to the
lock range of the PLL.
The detection band skew is a measure of how accu-
rately the largest detection band is centered about the
center frequency, fo. It is defined as (fmax + fmin -
2fo)/fo, where fmax and fmin are the frequencies corre-
sponding to the edges of the detection band. If neces-
sary, the detection band skew can be reduced to zero
by an optional centering adjustment. (See Optional
Controls.)
DESCRIPTION OF CIRCUIT CONTROLS
INPUT (Pins 11 and 14)
The input signal is applied to Pins 14 and/or 11 through
a coupling capacitor, Cc. These terminals are internally
biased at a dc level 2 volts above ground and they have
an input impedance level of approximately 20 kO.
TIMING RESISTOR R1 AND CAPACITOR C1 (Pins 1, 8, 9,
and 16)
The center frequency, fo, of each decoder section is set
by a resistor Rl and a capacitor Cl. R1A is connected
between Pins 1 and 16 in decoder section A, and Rl B
between Pins 8 and 9 of decoder section B. C1A is con-
nected from Pin 1 to ground, and Cl B from Pin 8 to
ground, as shown in Figure 4. R1 and Cl should be se·
lected for the desired center frequency by the expres-
sion fo "'" 1/R1Cl. For optimum temperature stability,
Rl should be selected such that 2 kO :::;; R1 :::;; 20 kO,
and the Rl Cl product should have sufficient stability
over the projected operating temperature range.
I
where Rl is in ohms and Cl is in farads.
The detection bandwidth is the frequency range cen-
tered about fo, within which an input signal larger than
the threshold voltage (typically 20 mV rms) will cause a
"logic zero" state at the output. The detection band-
width corresponds to the capture range of the PLL and
is determined by the low-pass bandwidth filter. The
bandwidth of the filter, as a percent of fo, can be deter-
mined by the approximation
~BW"", 1070
-i
foC2
where Vi is the input signal in volts, rms, and C2 is the
capacitance in J1.F at Pins 10 or 15.
Cc COUPLING CAPACITOR
CB BYPASS CAPACITOR
SI OPlN FOR 7V TO 12V
OPERATION CLOSED
FOR 4.SV TO 7V OPERATION
Figure 4. Circuit Connection Diagram
For decoder section A, the oscillator output can be ob-
tained at either Pin 1 or 16. Pin 16 is the oscillator
squarewave output which has a magnitude of approxi-
mately VCC - l.4V and an average dc level of VCC/2. A
1 kO load may be driven from this point. The voltage at
6-117







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