BUS CONTROLLER. M5L8288S Datasheet

M5L8288S CONTROLLER. Datasheet pdf. Equivalent


Mitsubishi M5L8288S
MITSUBISHI LSls
MSL8288S
BUS CONTROLLER FOR 8086/8088/8089 PROCESSORS
DESCRIPTION
The M5L82888 is a semiconductor integrated circuit consist-
ing of a bus controller and bus driver for the 8086 and 8088,
16-bit microprocessors. By using the status signals from the
CPU a Multibus (Intel trademark) control signal is gener-
ated.
FEATURES
• High-fanout outputs
Command output IOL=32mA, IOH=-5mA
Control output IOL= 16mA, IOH= -1 mA
• Advanced command outputs (AIOWC and AMWC
outputs)
• Low power dissipation
APPLICATION
Bus controller and bus driver for maximum mode operation
of th e 8086 an d 8088
FUNCTION
The M5L82888 is a bus controller and driver for maximum
mode operation of the 8086 and 8088 processors.
The command signals and control signals are decoded
by means of the 80- 82 outputs from the CPU and the con-
trol signals for I/O devices and memory are output.
The device can be used in the Multimaster mode in
which several CPUs acting as masters are connected to one
data bus. An input pin for the control signal AEN from an
8289 bus. arbiter is provided.
By using the M5L82888 as a bus controller, a highper-
formance 16-bit microcomputer system can be configured.
PIN CONFIGURATION (TOP VIEW)
1/0 BUS ~~S~ 10B~
Ve e (5V)
CLOCK INPUT ClK ~
STATUS INPUT S; ~
~tJ~IJ:~JT~'Ji DT/R~
s:: 17 ~MCE/PDEN
~~2~cnlfT~~~ ALE ~
01
b; 16 ~DEN DATA ENAB1.EOUTPUT
ADDRESS E~~~Gf AEN ~ 6
MEMORciu~~t~ MRDC~
I\)
ex>
eexn>
15 ~CEN ~~~~AND ENABLE
INTERRUPT
14 ~ INTA ACKNOWLEDGE
i\OV,4,NCEO _ _
MEMORY WRITE AMWC 4-
COMMAND OUTPUT
COMMAND OUTPUT
13 ~IORCggM~~~D OUTPUT
co~J~~b~~~1 MWTC ~
12 - AIOWC ¢?R~~~~~OM~~ND
OUTPUT
(OV)GND
11 ~ 10WC ggJt~~~ OUTPUT
'--------'
Outline 2081
BLOCK DIAGRAM
vee
I----------~
I
~rSTATUS INPUTS
1s,
STATUS
DECODER
COMMAND
SIGNAL
f-------IGENERATOR
I
7 MRDC MEMORY READ COMMAND OUTPUT
8 AMWC ~gv:~;~g ~~~p~~Y WRITE
9 MWfC MEMORY WRITE COMMAND OUTPUT
11 iC5WC 1/0 WRITE COMMAN D OUTPUT
12 AIOWC ~gXf~.f~g g8T~tfr
1/0 READ COMMAND OUTPUT
INTERRUPT ACKNOWLEDGE
COMMAND OUTPUT
COMMAND
OUTPUTS
1/0 BUS MODE INPUT lOB I
DATA TRANSMITIRECEIVE OUTPUT
CLOCK INPUT ClK 2
ADDRESS· ENABLE INPUT AEN 6
COMMAND ENABLE INPUT CEN 15
CONTROL 1-_ _--1 C~~~~~L
lOGIC
GENERATOR
DATA ENABLE OUTPUT
CONTROL
16 DEN ADDRESS LATCH ENABLE OUTPUT ) OUTPUTS
17 MCE/PDEN ~:~~~~RCA~S~~~~ ~~~~t~ ~~i~~il
I
L-----------4
GND
3-20
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M5L8288S Datasheet
Recommendation M5L8288S Datasheet
Part M5L8288S
Description BUS CONTROLLER
Feature M5L8288S; MITSUBISHI LSls MSL8288S BUS CONTROLLER FOR 8086/8088/8089 PROCESSORS DESCRIPTION The M5L82888 is .
Manufacture Mitsubishi
Datasheet
Download M5L8288S Datasheet




Mitsubishi M5L8288S
MITSUBISHI LSls
MSL8288S
BUS CONTROLLER FOR 8086/8088/8089 PROCESSORS
PIN DESCRIPTIONS
Input of
Pin Name
output
- - - -~--~~-~-,-
-~
- --
So, S" S2 Status input
Input
Functions
~--
These are connected to the CPU status output $0 ...... 5;.
The M5L828BS uses these signals to generate the proper timing command signals and control signals.
r - - - - - --_.~------~~-~
-~
CLK
Clock input
Input
. - - , - - - - - - - - --_._.-_..
All pins are provided with internal pull-up resistors.
Used to connect the clock generator M5L8284AP clock output elK.
All outputs of the M5L8288S change in synchronization with the clock input.
Provides the strobe signal output for the address latches.
This pin is connected to the STB pin of the M5L8282P or M5L8283P and used to latch the address from the
ALE
Address latch enable
output
Output
CPU. When using any other address latch, the fonowing conditions must be satisfied.
l. The enable input must be active high.
2. Data reading is always performed while the enable input is high.
DEN
Data enable
3. The latching operation is performed as the enable input goes from high to low.
Provides the data enable signal for the local bus or a data transceiver on the system bus.
Output
Operates in active high mode.
- - f - - - - - r------------~---
Controls the flow of data between CPU and memory or peripheral t/O devices.
--
-
DTIR
--~
AEN
Data transmit/receive
control output
Output
When this pin is high, the CPU can write data to the peripheral devices. When it is low, it can read data
from the peripheral devices.
+~~-~~- It is connected to the transmit input T of the M5L8286P or M5L8287P bus transceivers.
1 - - - - - - - - - - - --~~--~---
Address enable input
Input
When the lOB input is low and the AEN input is set to high, all command outputs are put in the high-
-- ------
--
impedance state. When the lOB input is high, there is no effect on the tORC, 10WC, AIOWC, and INTA out.-
puts, the command output other than these four going into the high-impedance state.
None of the command outputs will go low until at least 115ns after AEN transits from high to low.
c - - - - - - -~-------
----
~---
CEN
Command enable input Input
- - - I------.~---
--~
lOB
Input/output bus mode
input
I Input
When this pin is set to low, all command outputs and DEN are prohibited by the PDEN control output (not
high-impedance state). When set to high, the above outputs are enabled.
~~~
I When this pin is set to high, the M5L8288S fUnctions in the I/O bus mode, and when set to low it functions in
the system bus mode. (The 1/0 bus mode and system bus mode are described in the functional
description)
-~
---
AIOWC
Advanced I/O write
command output
Output
The AIOWe issues an lID Write Command earlier in the machine cycle to give I/O devices an early indica-
tion of a write instruction its timing is the same as a read command signal. Active low.
--
---
10WC
I/O write command
output
Instructs an 110 device to read the data on the data bus. Active low.
Output
--
10RC
---
AMWC
---
MWTC
---
MRDC
I/O read command
output
Advanced write
Output Instructs an I/O device to drive its data onto the data bus. Active low.
-~-
i~sue;-;;;'emory ~-;;;;;f------rThe AMWC
write command earlier in the machine cycle to give memory devices an
command output
-
Output
Memory write command
Output
output
c------~---,-.-----~
Memory read command
Output
output
• indication of a write instruction. Its timing is the same as a read command signal. Active low.
I Provides a write instruction to memory for the current data on the bus.
Active low.
-
Provides an output instruction to memory for the present data on the bus.
Active low.
~~-
--
INTA
MCEI
---
PDEN
Interrupt acknowledge
command output
Master cascade
Enable output!
Peripheral data
Enable output
Output
Output
This output informs an interrupting device that it has accepted the interrupt. outputting a vector address out-
--
put instruction to the data bus. IORC operates in the same manner for interrupt cycles. Active low.
----
This output pin has two functions.
1. When the lOB input is set to low:
The MCE function is enabled. The signal acts as the enable signal which allows a slave PIC
(M5L8259AP) to read the cascade address output to the bus by the master PIC during an interrupt sequ-
ence. Active high.
2. When the lOB input is set to high:
--
The PDEN function is enabled. This output provides the enable signal to the data bus transceiver con-
nected to the liD interface bus when an instruction occurs (lORC, lOWe, Alowe, INTA). Operates the
same way as DEN with respect to the system bus.
a
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3-21



Mitsubishi M5L8288S
MITSUBISHI LSls
MSL8288S
BUS CONTROLLER FOR 8086/8088/8089 PROCESSORS
FUNCTIONAL DESCRIPTION
The state of the command outputs and control outputs are
Sa -determined by the CPU status outputs
82. The table
summarizes the states of the outputs 80 - 82 and their cor-
responding valid command output names.
Depending upon whether the M5L82888 is in the I/O bus
mode or system bus mode, the command output sequence
will vary.
STATUS INPUTS AND COMMAND OUTPUTS RELATIONSHIPS
S, 5,
LL
LL
LH
LH
HL
HL
.H H
HH
So 8086, BOB8 status
L Interrupt acknowledge
H Data read from an 110 port
L Data write to an I/O port
H Halt
L Instruction fetch
H Read data from memory
L Write data to memory
H Passive state
Valid command output name
INTA
IORC
IOWC,AIOWC
-
MRDC
MRDC
MWTC, AMWC
-
1. 1/0 bus mode operation
When lOB is high, the M5L82888 function in the 1/0 bus
mode.
In the I/O Bus mode all I/O command lines (IORC, 10WC,
AIOWC, INTA) are always enabled (i.e., not dependent on
AEN). When an 1/0 command is initiated by the processor,
the 8288 immediately activates the command lines using
PDEN and DT/R to control the 110 bus transceiver. The 110
command lines should not be used to control the system bus
in this configuration because no arbitration is present. This
mode allows one 8288 Bus Controller to handle two external
busses. No waiting is involved when the CPU wants to gain
access to the 1/0 bus. Normal memory access requires a
"Bus Ready" signal (AEN LOW) before it will proceed. It is
advantageous to use the lOB mode if 1/0 or peripherals de-
dicated to one processor exist in a multi-processor system.
the AEN Line is activated (LOW). This mode assumes bus
arbitration logic will inform the bus controller (on the AEN
line) when the bus is free for use. Both memory and 1/0
commands wait for bus arbitration. This mode is used when
only one bus exists. Here, both 1/0 and memory are shared
by more than one processor.
3. AMWC and AIOWC outputs
With respect to the normal write control Signals MWTC and
10WC, the advanced-write command signals AMWC and
AIOWC transit low one clock cycle earlier and remain low
for two clock cycles.
These Signals are used with peripheral devices or static
RAM devices which require a long write pulse, so that the
CPU does not go into an unnecessarily wait cycle.
2. System bus mode operation
When lOB is set to low, the M5L82888 enters the system bus
mode. In this mode no command is issued until 115 ns after
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