DMA CONTROLLER. M5M82C37AFP-4 Datasheet

M5M82C37AFP-4 CONTROLLER. Datasheet pdf. Equivalent


Mitsubishi M5M82C37AFP-4
MITSUBISHI LSls
MSM82C37AFP,-4,-S
CMOS PROGRAMMABLE DMA CONTROLLER
DESCRIPTION
The M5M82C37AFP is a programmable 4-channel DMA
(Direct Memory Access) controller. This device is specially
designed to simplify data transfer at high trasfer rate for
microcomputer systems.
Fabricated using the silicon-gate CMOS technology, the
M5M82C37AFP operates using a single 5V power supply.
FEATURES
• 5V single supply, single TTL clock
• Four channel DMA controls with priority DMA request
acknowledge functions
• DMA enable/disable, automatic initialization enable/dis-
able, address increment/decrement programmability for
each cannel
• Programmable DREQ input and DACK output logic
polarity
• Direct connecting permits easy DMA channel expan-
sion.
• Memory to memory data transfer
• EOP input/output permits DMA operation completion
check as well as forcibly completing DMA operation.
APPLICATION
• DMA control of peripheral equipment such as floppy
diskettes and CRT terminals that require high-speed
data transfer.
PIN CONFIGURATION (TOP VIEW)
I/O READ
INPUT/OUTPUT lOR -
:~~~~g~TPUT lOW -
~fAMDO~GTPUT MEMR -
W~\"1-nYUTPUTMEMW -
NON-USABLE NU -
READY INPUT READY -
HOLD
ACKNOWLEDGE INPUT HlDA -
~~~~3~S STROBE ADSTB _
~E~~3~S ENABLE
HOLD REQUEST
OUTPUT
CHIP SELECT INPUT
CLOCK INPUT
AEN -
CS -
ClK _
1
2
3
4
5
6
7
B
9
11
12
40 - A'l
39 - As ADDRESS
38 _ Asj OUTPUTS
37 - A.
36 - EOP ~~tu~:o~~g~iss
35 - A3l
34 - A, ADDRESS INPUTS/
33 - A, j OUTPUTS
32 - Ao
Vee (5V)
RESET INPUT RESET -
Ag~,;oWLEDGE J DAC K, -
OUTPUTS
I DACK3 -
13
14
15
DMA
REQUESTS
INPUTS
IDREQ3- 16
DREQ,- 17
DREQ,- 18
DREQo- 19
25 -
24 -
23 -
22 _
Vss (OV) ""-l_ _ _ _ _....r2.1... -
DACKo l ~~:NOWLEDGE
DACK, [OUTPUTS
DBsl
DB DATA INPUTS/
s [OUTPUTS
DB,
Outline 40P2R
BLOCK DIAGRAM
::: f;: --- ----- --C-~-~-RRE-~'---!-~~~-------- -
DATA
BUS
BUFFER
COUNT
REGISTER!
COUNTER
COUNT
REGISTER!
COUNTER
DMA
DREQo
DACKo
DREQ,
DACK,
DREQ,
DACK,
DREQ3
15 DACK3
ClK
A,
As
CURRENT
As
A4
ADDRESS
ADDRESS
BASE
ADDRESS
A3
BUS
REGISTER!
REGISTER
A, BUFFER COUNTER
A,
Ao
BUS
HlDA
AEN
ADSTB
MEMW
MEMR
lOW
lOR
- - - - - - -__ - - - - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - - - l
• MITSUBISHI
. . . . ELECTRIC
5-35


M5M82C37AFP-4 Datasheet
Recommendation M5M82C37AFP-4 Datasheet
Part M5M82C37AFP-4
Description CMOS PROGRAMMABLE DMA CONTROLLER
Feature M5M82C37AFP-4; MITSUBISHI LSls MSM82C37AFP,-4,-S CMOS PROGRAMMABLE DMA CONTROLLER DESCRIPTION The M5M82C37AFP is .
Manufacture Mitsubishi
Datasheet
Download M5M82C37AFP-4 Datasheet




Mitsubishi M5M82C37AFP-4
MITSUBISHI LSls
MSM82C37AFP,·4,·S
CMOS PROGRAMMABLE DMA CONTROLLER
FUNCTION
M5M82C37AFP is a programmable DMA controller LSI
used in microprocessor systems.
This device basically consists of a DMA request control
block for acknowledging DMA requests, a CPU interface
for exchanging data and commands with the CPU, a timing
control circuit for controlling each of the various types of
timing, and a register for holding and counting DMA
addresses and number of transfer words.
After setting the transfer mode, starting address, and byte
number in each of the registers and when a DMA request
is made to an unmasked channel, the M5M82C37AFP re-
quires use of the bus to the CPU. When the HLDA signal is
received from the CPU, the DMA acknowledge signal is
sent to DMA requesting channel with the highest priority
and begins DMA operation.
During DMA operation, the contents of the low-byte of the
transfer memory address are output through A7 - Aa. Every
time a change in the high-order 8-bit values is necessitated
immediately after DMA operation has begun or due to bor-
rowing or decrement during DMA operation, the change is
output via pins DB7 - DBa to the externally mounted latch
circuit. After the address is transmitted, read and write sig-
nals are sent to the memories and peripherals activating
DMA transfer.
ABSOLUTE MAXIMUM RATINGS
Symbol
Vee
V,
Va
Top,
Tsta
Parameter
Supply voltage
Input voltage
Output voltage
Operating free-air temperature range
Storage temperature
Conditions
With respect to vss
Limits
-0.3-7
-0. 3-Vee+0. 3
-0. 3-Vee+0. 3
-20-75
-65-150
Unit
V
V
V
°e
°e
RECOMMENDED OPERATING CONDITIONS (Ta=-20-75'C, unless otherwise noted)
Symbol
Vee
Vss
Parameter
Supply voltage
Supply voltagelGND)
Limits
Min I Typ I Max
4,5 I 5 I 5.5
I0 I
Unit
V
V
ELECTRICAL CHARCTERISTICS (Ta=-20-75°C, Vcc=5V±10%, Vss=OV, unless otherwise noted)
Symbol
V ,H
V ,L
V OH
Parameter
Hign-Ievel input voltage
LOW-level input voltage
High·level output voltage
VOL
I,
loz
lee
LOW-level output voltage
Input current
Off-state output current
Supply current
Test conditions
IOH=-200,uA
IOH=-100,uA(HRQ only)
10L=2. OmA( data bus)
10L=3. 2mA( other outputs)
V,=O-VCC
V,=O-VCC
V,H=VCC, Vll=Vss, fCLK=l/tc( ¢)min.
Min
2.0
-0.3
2.4
3.2
-10
-10
Limits
Typ
Max
Vcc+O.3
0.8
0.45
+10
+10
15
Unit
V
V
V
V
V
/LA
/LA
rnA
5-36
• MITSUBISHI
.... ELECTRIC



Mitsubishi M5M82C37AFP-4
MITSUBISHI LSls
MSM82C37AFP,.4,·S
CMOS PROGRAMMABLE DMA CONTROLLER
TIMING REQUIREMENTS (Ta=-20-75'C , Vcc=5V±10%, Vss=ov, unless otherwise noted)
(i) SLAVE MODE
Symbol
Parameter
tSU(CS-R)
tSUCA-R)
tsu(CS-w)
Address setup time before read
cs setup time before write
tSU(A-W)
Address setup time before write
tsu(OQ-w)
Data setup time before write
th(R-cs)
th(R-A)
Address hold time after read
thcw-cs)
CS hold time after write
th(W-A)
Address hold after write
theW-DQ)
tWCR)
Data hold after write
Read pulse width
tw(w)
Write pulse width
tWCRESET)
Reset pulse width
tSU(VCC-RESET) Vee setup time before to reset
tSU(RESET-R) Reset setup time before read
tSU(RESET-W) Reset setup time before Write
Alternate
symbol
M5M82C37AFP
Min Max
Limits
M5M82C37AFP-4
Min Max
M5M82C37AFP-5
Min Max
Unit
TAR
Tcw
TAW
Tow
TRA
50 50 50(0)
~H------200
200
20
0
-
-
-
r---
150
1
-
150
r--- 150
100
000
ns
ns _..-
- - 1 - -n-s- . - -
-~-~----
ns
"--- - -
ns
Twc
TWA
Two
TRW
Twws
T RSTW
T RSTD
20
20
30
300
200
300
500
IT R S T S
2tc (.)
20
20
30
250 --
200
300
500
2tc (. )
._-
20 (0)
20(0)
30 (0)
200
160
300
500
2tc (. )
- - -ns- -
ns
- _ . _ns- - -
ns
---
- ns.. --~---
ns
ns -
ns
(ii) DMA MODE
Symbol
Parameter
tW (' )
tw(. )
Clock high-level pulse width
Clock low-level pulse width
tce. )
Clock period
tSU(EOP-<P ) External EOP setup time before clock
tw(eop)
External EOP pulse width
tS U (OREQ-1> ) DREQ setup time before clock
tsu< READY- '" ) READY setup time before clock
the 1> -READY) READY hold time before clock
tSU(HLDA- "')
tSU(DQ-MEMR)
th(MEMR_DQ)
HLDA setup time before clock
Data setup time before MEMR
Data hold time after MEMR
Note
A.C Testing waveform
Input pulse level
Input pulse rise time
Input pulse fall time
Reference level input
Output
o. 45-2. 4V
10ns
10ns
V,H =2V, V,L=0. 8V
VoH =2V, VOL=0. 8V
Alternate
symbol
TCH
TCL
Tcy
TEPS
T EPW
Tos
T Rs
TRH
T Hs
TlDs
TIDH
M5M82C37AFP
Min Max
120
150
320
60
300
0
100
20
100
250
0
Limits
M5M82C37AFP-4
Min Max
100
110
250
45
225
0
60
20
75
190
a
M5M82C37AFP-5
Min Max
80
68
200
40
220
0
60
20
75
170
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
III
• MITSUBISHI
;"ELECTRIC
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