CRT CONTROLLER. M58992P Datasheet

M58992P CONTROLLER. Datasheet pdf. Equivalent

M58992P Datasheet
Recommendation M58992P Datasheet
Part M58992P
Description CMOS CRT CONTROLLER
Feature M58992P; MITSUBISHI LSls MS8992P CMOS CRT CONTROLLER DESCRIPTION The M58992P is a raster scan type CRT inte.
Manufacture Mitsubishi
Datasheet
Download M58992P Datasheet




Mitsubishi M58992P
MITSUBISHI LSls
MS8992P
CMOS CRT CONTROLLER
DESCRIPTION
The M58992P is a raster scan type CRT interface device,
fabricated using silicon gate CMOS technology. This LSI is
a one-chip type high-performance video display generator
having the timing signal generator and attribute circuits re-
quired for CRT display so as to allow system configuration
with a small number of components.
FEATURES
• Single 5V supply voltage.
• Can generate· video display using simple external
circuit
• 10 programmable display modes
• Some mode conditionally allows mixed use with other
mode.
• Color display is programmable to use either 8 or 16
colors.
• The R, G and B Signals are provided as video output
signals.
• Can superimpose on TV screen
• A 16K or 64K DRAM is used as the video RAM under
control of the built-in DRAM controller.
• The video RAM area can be used concurrently for stor-
age of display data and microprocessor program.
• Paging and scrolling are possible.
• Cursor control; blinking, blanking, underline and reverse
characters are possible.
• Light pen input control function is provided.
• Various interrupts generating function is provided.
APPLICATION
Display unit using home TV set or monitor TV set
FUNCTION
The information or data to be displayed on the screen is
written in the video RAM by the microprocessor. The
M58992P can read the video RAM in the order of the CRT
scan, and can generate synchronization signal for a CRT.
PIN CONFIGURATION (TOP VIEW)
(OV)V55
DAD7 - 2
DAD.- 3
MULTIPLEXED
DRAM
ADDRESS/DATA
BUS
DADs -
DAD, -
DAD3 -
DAD2 -
4
5
6
7
ROW ADDRESS DADo - 9
STROBE OUTPUT RAS - 10
~~~g~~ ~~~~G~S CAS - 11
WRITE ENABLE WE - 12
I :OU:~:O OUTPUTS ~:
B-15
1- 16
BURST OUTPUT BRST - 17
CLOCK B
CLOCK M MClK - 19
SYSTEM CLOCK ClK --+ 20
BD~~G~G BLANK - 21
LIGHT PEN l TPEN --+ 22
STROBE INPUT RAo _ 23
~~~~~K{6~ IRA, - 24
RASTER ADDRESS RA2 - 25
OUTPUTS
RA3 _ 26
ADDRESS BUS
47 --+ READY READY OUTPUT
46 - RESET RESET INPUT
45 --+ INTR ~~~~r~nUTPUT
44 - loiM IO/MEMORY INPUT
CHIP SELECT
INPUT
READ INPUT
WRITE INPUT
CODE DATA jCDRD, -
READ OUTPUTS) CDRD2 _
~ft~g1~~8fDE CALT -
HORIZONTAL HSYNC _
SYNCHRONIZE - -
OUTPUT
VSYNC -
~~~~~~6NIZE (Ov) v 55
OUTPUT
27
28
29
30
31
Outline
64P48
DATA BUS
5-102
• MITSUBISHI
.... ELECTRIC



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I----START DISPLAY
ADDRESS MODE COMMAND COLOR
REGISTER
REGISTER
REGISTER
REGISTER
~
VIDEO AND
ATTRIBUTE
DATA
CONTROLLER
88
.. INTERNALBUS
X
STATUS
REGISTER
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LTPEN
DATA BUS BUFFER
IIIII111
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D~ D~ D~ D~
MICROPROCESSOR
COMMAND DECODER
MICROPROCESSOR
BUS INTERFACE
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WR RD CS loiM RESET
45 I-{ 47
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INTR READY
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Mitsubishi M58992P
MITSUBISHI LSls
MS8992P
CMOS CRT CONTROLLER
PIN DESCRIPTION
Pin
Name
Input/output
Functions
DAD7~
DADo
Multiplexed
DRAM address
Idata bus
Causes data input from DRAM or data output for writing in DRAM by output of mltiplexed row and col-
Input/output
umn address to DRAM.
-~
RAS
Row address
strobe output
Output
~
DRAM address input is latched at falling edge of RAS.
-~
CAS
~
WE
Column address
strobe output
Write enable output
Output
DRAM address input is latched at falling edge of CAS.
Output
Data from microprocessor is written in DRAM when this signal is "L".
R Video output R
G Video output G
TTL level output of video signals R, G and 8.
B Video output B
Output
-~
I Video output luminance
Auxiliary output for R, G and B. By externC\1 Combination with R, G and B, up to 16 colors can be dis-
played.
1= "H" indicates high luminance.
BRST
Burst output
Output
Signal to indicate color burst signal position or sUb-carrier frequency phase-modulated by RGB in case
of NTSC system.
BClK
Clock B
MClK
Clock M
Output
Output
Frequency at 114 of clock input. Subcarrier frequency in NTSC color system.
--
Internal timing clock. Indicates DRAM access by the M58992P for display when this signal is "L" in the
text 1, text 2, graphic 1, graphic 2, graphic 3 or graphic 5 mode.
ClK
---
BLANK
System clock
Blanking output
Input
Output
14.31818MHz for display using NTSC system.
Indicates around the synchronizing pulse in horizontal or vertical blanking period of the M58992P.
lTPEN
Light pen strobe input
Input
Signal to latch internal address value.
RA3~
RAo
Character generator
raster address
outputs
Output
Least significant 4 bits of address for use of character generater to be used in text mode.
---
CDRD1
---
CDRD2
Code data read outputs
Output
Signal to control external circuit for input of display code pattern to the M58992P.
---
--~
CDRD1 is the timing for direct data input from DRAM to the M58992P, and CDRD2 is the timing for input
from character generator.
CAlT
Character code
latch output
---
HSYNC
Horizontal
synchronize 'putput
----
VSYNC
Vertical
synchronize output
Output
Signal to cause external latching of character generator pointer output from DRAM.
-
Open drain
output
Setting synchronizing signal input mode by command causes no generation of internal synchronizing sig~
nal but internal counter reset by external signal.
5-104
• MITSUBISHI
..... ELECTRIC







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